A latch-type comparator with a dynamic bias preamplifier is implemented in a 65nm CMOS process. The dynamic bias with a tail capacitor is simple to implement and ensures that the pre-amplifier output nodes are only partially discharged to reduce the energy consumption. The comparator is analyzed and compared to its prior-art in terms of energy consumption and input referred noise voltage. First-order equations are presented that show how to optimize the pre-amplifier for low noise and high gain. Both the dynamic bias comparator and the prior-art are implemented on the same die and measurements show that the dynamic bias can reduce the average energy consumption by about a factor 2.5 for the same input-equivalent noise at an input common mode level of half the supply voltage.

A dynamic bias pre-amplifier based latch type comparator is designed in a 65nm CMOS process. Its performance is compared with the double-tail latch-type comparator fabricated on the same chip in terms of energy consumption, input referred noise and speed. Measurements demonstrate that the proposed dynamic bias pre-amplifier based comparator consumes 2.8 times less energy per comparator operation with a modest reduction in input referred noise and 40% increase in CLK-Q delay for small differential input voltages.

Class-D amplifiers switch high voltages and currents at high frequencies and hence produce electromagnetic interference (EMI). This work presents a technique to reduce the high frequency ripple, which is still present after the output filter. A Class-A ripple reduction amplifier is put in parallel to the output of the Class-D amplifier, each having their own feedback loop with digital filters. High ripple reduction loop gain is achieved at the PWM frequency by using a resonator as digital loop filter. Dissipation in the Class-A amplifier is reduced by using a low common-mode signaling technique. Commonmode and differential-mode switching components at the PWM frequency are reduced by 27 dB and 18 dB respectively. Total system efficiency is 79% at 40 W output power.

This work presents an analytical method to design a stable loop filter for a noise shaper with parasitic delays or poles in the loop. This method does not require an increase in the order of the loop or extra feedback paths and keeps the original poles and zeros of the noise-transfer function at the same location. The method has been applied to a low-pass loop filter with a parasitic unit delay and a band-pass loop filter with either three unit delays or a high-frequency pole, obtaining stable loop filters in all three cases.