Abstract. This article gives a survey on different methods of formal synthesis. We define what we mean by the term formal synthesis and delimit it from the other formal methods that can also be used to guarantee the correctness of an implementation. A possible classification scheme for formal synthesis methods is then introduced, based on which some significant research activities are classified and summarized. We also briefly introduce our own approach towards the formal synthesis of hardware. Finally, we compare these approaches from different points of view.

Abstract. This article describes the embedding of high level synthesis algorithms in HOL. For given standard synthesis steps, we describe, how its data can be mapped to terms in HOL and the synthesis process be expressed by means of a logical derivation. In contrast to post-synthesis veri cation techniques our approach is constructive in a sense that the proof is derived during synthesis rather than \guessed" afterwards. Therefore one does not get into the hardship of NP-completeness or undecidability. Our approach ensures correctness based on the HOL system and is also performed fully automatically.

Abstract| F ormal synthesis has become an interesting alternative towards post-synthesis veri cation. Formal synthesis means integrating formal validation within the synthesis process by performing synthesis via rule applications. The practical applicability of formal synthesis very much depends on the e ciency of the underlying rules. This paper gives a case study about the complexity of formal synthesis programs. Experiments with two realistic-sized benchmark circuits were performed using the formal synthesis system HASH Higher order logic Applied to Synthesis of Hardware. HASH provides means for representing and transforming circuits in a secure and logically sound manner. Furthermore, arbitrary synthesis procedures can be invoked to achieve high quality of designs. In this paper, the implementation of a formal scheduling step is used to illustrate e ciency considerations related to formal synthesis.

Abstract. In our terminology, the term "formal synthesis" stands for a synthesis process where the implementation is derived from the specification by applying elementary mathematical rules within a theorem prover. As a result the implementation is guaranteed to be correct. In this paper we introduce a new methodology to formally derive register-transfer structures from descriptions at the algorithmic level via program transformations. Some experimental results at the end of the paper show how the run-time complexity of the synthesis process in our approach could be.