Abstract. This article gives a survey on different methods of formal synthesis. We define what we mean by the term formal synthesis and delimit it from the other formal methods that can also be used to guarantee the correctness of an implementation. A possible classification scheme for formal synthesis methods is then introduced, based on which some significant research activities are classified and summarized. We also briefly introduce our own approach towards the formal synthesis of hardware. Finally, we compare these approaches from different points of view.

Abstract. This article describes the embedding of high level synthesis algorithms in HOL. For given standard synthesis steps, we describe, how its data can be mapped to terms in HOL and the synthesis process be expressed by means of a logical derivation. In contrast to post-synthesis veri cation techniques our approach is constructive in a sense that the proof is derived during synthesis rather than \guessed" afterwards. Therefore one does not get into the hardship of NP-completeness or undecidability. Our approach ensures correctness based on the HOL system and is also performed fully automatically.

Abstract| F ormal synthesis has become an interesting alternative towards post-synthesis veri cation. Formal synthesis means integrating formal validation within the synthesis process by performing synthesis via rule applications. The practical applicability of formal synthesis very much depends on the e ciency of the underlying rules. This paper gives a case study about the complexity of formal synthesis programs. Experiments with two realistic-sized benchmark circuits were performed using the formal synthesis system HASH Higher order logic Applied to Synthesis of Hardware. HASH provides means for representing and transforming circuits in a secure and logically sound manner. Furthermore, arbitrary synthesis procedures can be invoked to achieve high quality of designs. In this paper, the implementation of a formal scheduling step is used to illustrate e ciency considerations related to formal synthesis.

Physolator is Java based physics simulation framework. Physolator supports an object oriented style for building physical models. This article describes Physolators core architecture and it explains how the framework architecture contributes to building physical simulations in a modular, object oriented style.

Abstract. This paper introduces a general scheme for formally embedding high level synthesis by formulating its basic steps as transformations within higher order logic. A functional representation of a data ow graph is successively re ned by means of generic logical transformations. Algorithms that are based on logical transformations guarantee \correctness by design". They not only construct an implementation but also derive the proof for its formal correctness, on the y. An extra postsynthesis-veri cation step becomes obsolete. The logical transformations presented in this paper form a framework for formally embedding existing high-level-synthesis procedures.