On the efficiency of formal synthesis-experimental results

Blumenröhr, Christian; Eisenbiegler, Dirk; Schmid, Detlef

doi:10.1109/43.739056

Cited by 6 publications

(3 citation statements)

References 17 publications

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“…Several formal synthesis systems have been introduced such as, TRuby [12] and HASH [2]. Kumar et al [9] present an interesting summary and classification of formal synthesis research activities.…”

Section: Related Workmentioning

confidence: 99%

Automated formal synthesis of Wallace Tree multipliers

Hasan

Kort

2007

2007 50th Midwest Symposium on Circuits and Systems

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In this paper, we present a formal synthesis methodology that is capable of performing correct synthesis at almost all levels of abstraction and can be adapted to be used for most of the combinational digital circuits irrespective of their size and complexity. The proposed methodology calls for proving the correctness-preserving characteristic for the transformations that are required in the synthesis of a particular digital circuit in a higher-order-logic theorem prover. These correctnesspreserving transformation proofs can then be used to automatically verify the correctness of the corresponding synthesis process within the theorem prover in an automated way. For illustration purposes, we present the construction of an automated formal synthesis tool for Wallace Tree multipliers based on our methodology.

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Section: Related Workmentioning

confidence: 99%

Automated formal synthesis of Wallace Tree multipliers

Hasan

Kort

2007

2007 50th Midwest Symposium on Circuits and Systems

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“…As compared to the original HOL system, it has been made more efficient by changing the term representation and adding two core functions. See [22] for a detailed description and discussion about this. As we have demonstrated in the paper, the result of our synthesis process is a guaranteed correct implementation.…”

Section: Fig 6 Time [S] For Synthesis Experimentsmentioning

confidence: 99%

Formal Synthesis at the Algorithmic Level

Blumenröhr

Sabelfeld

1999

Lecture Notes in Computer Science

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Abstract. In our terminology, the term "formal synthesis" stands for a synthesis process where the implementation is derived from the specification by applying elementary mathematical rules within a theorem prover. As a result the implementation is guaranteed to be correct. In this paper we introduce a new methodology to formally derive register-transfer structures from descriptions at the algorithmic level via program transformations. Some experimental results at the end of the paper show how the run-time complexity of the synthesis process in our approach could be.

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“…Exploiting the idea of separating the design space exploration from the formal derivation, the HASH project [3] defines a set of guidelines to formalize both the behavior to be implemented and the design decisions taken as higher-order λ-expressions. The system uses the theorem prover HOL to decide the soundness of those decisions.…”

Section: Related Researchmentioning

confidence: 99%

Efficient verification of scheduling, allocation and binding in high-level synthesis

Mendias

Hermida

Molina

et al.

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools

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This paper presents an efficient method to solve an important aspect of the high-level verification problem: the formal verification of RT-level implementations (datapath + controller), obtained from algorithmic-level specifications by high-level synthesis tools. The method consists in replicating external, and potentially incorrect, design processes within a mathematical framework, giving as a result the proof of correctness or the set of design decisions that led to errors. As the computational complexity is a major problem in formal verification, the formal framework is based in an ad hoc formal theory. The moderate complexity achieved, has been confirmed by a detailed experimental study, which shows that our method can verify complex designs overloading the highlevel design-cycle only minimally.

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On the efficiency of formal synthesis-experimental results

Cited by 6 publications

References 17 publications

Automated formal synthesis of Wallace Tree multipliers

Automated formal synthesis of Wallace Tree multipliers

Formal Synthesis at the Algorithmic Level

Efficient verification of scheduling, allocation and binding in high-level synthesis

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