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One of the hot topics in the Extreme Ultra-Violet (EUV) mask fabrication process is the requirement to produce multilayer blanks without any printing defects. As the potential of experimental studies is still limited, a predictive simulation of EUV lithography is an important step on the way to meet this requirement.The simulator tool SOLID-EUV 4 is extended to deal with defective multilayers. The simulation is divided into two regions, the finite-difference timeñdomain (FDTD) method for the absorber part and the simulation of the multilayer reflectivity by the Fresnel-method. To take the defects into account the multilayer is divided into segments, which include the defect, and the reflectivity is calculated for each segment. For calculating the multilayer stack for each segment the defects are assumed to be Gaussian shaped. For the complete computation of the reflected light from the EUV mask a coupling of the two methods is realized.This paper presents case studies using the lithography simulator tool SOLID-EUV 4 with the new defective multilayer simulation part, to analyse the printability of defects. The impact of the defect size, horizontal and vertical defect position within the multilayer, and the influence of the layer deposition process is analysed. The most influential defect parameters are identified. One defect with an influence which tends to be printed is taken and combined with typical mask structures, such as isolated lines, lines and spaces and contact holes. The process windows of the mask structures for various defect positions are analysed. These simulations can be used to develop strategies to handle such defects.

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E-Beam Lithography is still the driving technology for semiconductor manufacturing of critical levels at the 45nm node. Mask costs, yields and representation of the mask on wafer are important factors to consider. Mask-less E-beam lithography is being considered, but major manufacturing is still done by scanner technology. Therefore the same emphasis on modeling applied in the 1990's on the wafer is now being applied to mask technologies to drive down costs, improve yields and to develop viable mask to wafer transfer patterns.Yield is ultimately connected to process latitude, which is limited by a variety of electron-material interaction issues. As in the optical world, the question is how to maximize the process window considering all the systematic and statistical error sources. Simulation can be used to find out the magnitude of yield limiting effects, and to evaluate the contributing error sources such as PEC file contributions. Film stacks are now becoming an important contributor to statistical error due to technologies such as tri-tone attenuated masks that place a thin layer of chrome over MoSi.In this paper we will compare the SELID E-beam simulation to cross-sections of line-space and contact patterns. Demonstrations of simulation to real data and the use of simulation to further evaluate process window to enhance the learning mode during development cycles will be presented.