This paper describes a four-channel piezo driver chip for use in active structural health monitoring. Each channel can drive a piezoelectric transducer with a continuous wave signal of ±36 V and 780 kHz. The waveform is synthesized using filtered pulse width modulation (PWM), where the pulse transition times are pre-computed through a least square optimization problem. A calibration technique is introduced to achieve subnanosecond timing accuracy and -40.5 dB signal distortion. A 13 mm 2 proof-of-concept IC was fabricated in a 0.25 µ µ µ µm BCD process and evaluated within an application test bed.

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The slow progress of the 157nm-F 2 laser exposure tool development results in broad adaptation of high numerical aperture (NA>0.8) 193nm-ArF lithography for the 65nm-node production solution. This decision, however, forces lithographers to increase dependency on very aggressive RET technologies. This in turn demands mask making capabilities the industry has never faced before such as 100nm (@4X on mask scale) size Sub Resolution Assist Features (SRAF).This report covers our early work on our mask making capability development for the 65nm-node process technology development cycle for production in 2005. Our report includes the 65nm node mask technology capability development status for mask CD and registration dimensions control, current inspection capability/issues and development efforts for critical layer masks with aggressive RET (especially of EAPSM with SRAF).

Sub-wavelength lithography used for today's 130nm and 90nm node devices requires new approaches to both lithography processes and chip design. Reticle complexity has increased as OPC and Phase Shift techniques are used to improve lithography process windows at smaller process nodes. Among new revolutionary design implementations specifically for metal layers, the X Architecture is an interconnect architecture based on the pervasive use of diagonal wiring, reducing total chip wire length by an average 20% and via count by an average of 30%, resulting in simultaneous improvements in chip speed, power, and cost.An important consideration for implementation of any new IC manufacturing process is early verification that the new process, technology, or design has stable manufacturability in a production environment. To perform this verification for X Architecture reticle inspectability, an investigation was launched with the goal to optimize reticle inspection for X Architecture metal layers. The TeraStar reticle inspection system was used inspect two sources of X Architecture metal 4 and metal 5 layers, both employing X Architecture design data.The reticle inspection investigation of the new X Architecture represents a new level of cooperation between the design and manufacturing communities. This is an important step forward for both X Architecture and the industry as we look into the future challenges of designing, inspecting and building next generation semiconductors. The implementation of X Architecture has demonstrated key advantages in the areas of device real estate and power consumption. However, the beneficial diagonal structures have been shown to be problematic on older generation reticle inspection systems. Development of the TeraStar SLF77 introduced in 2001 included the test case usage of many diagonal reticle patterns. This resulted in the capability of successful X Architecture database mode reticle inspection using standard algorithms with no modifications. This paper will present the results of these reticle inspections and will report the overall inspectability of the X Architecture design and the viability of TeraStar reticle inspection on these reticles in a production environment. X ARCHITECTURE OVERVIEWMost lithographers are familiar with the traditional Manhattan form of integrated circuit wiring. X Architecture as described by one of the inventors S. Tieg is based on the simple mathematical truth that the shortest path from A to B is along the diagonal. The architecture uses large amounts of diagonal features on metal layers 4 and above, rotating them 180 degrees by layer. X Architecture defines metal layers 1-3 to be Manhattan to preserve the investment in libraries and intellectual property, however on metal 2 and 3, small amounts of diagonal wires are used to further reduce vias and overall wire length. Demonstrated benefits of using X Architecture are 20% or more less interconnects and 30% fewer vias, which translate into simultaneously, smaller, faster, cheaper and lower power chips. X A...