Deep Level Transient Spectroscopy (DLTS) has been applied to Metal-Oxide-Semiconductor (MOS) capacitors fabricated on crystalline silicon n-and p-type substrates, with a SiO 2 or a SiO 2 /SiN x passivation stack, covered by an Al gate. It is shown that similar interface state distributions are obtained in both cases, from which it is concluded that the SiN x deposition does not degrade the interface. It is also shown that a rather large density of dangling bond defects is present at the Si/SiO 2 interface, which is related to the absence of a post metallization forming gas annealing.
Low frequency direct plasma-enhanced chemical vapor deposited Si–SiNx interface properties with and without NH3 plasma pretreatment, with and without rapid thermal annealing (RTA) have been investigated with deep-level transient spectroscopy (DLTS) on both n- and p-type monocrystalline silicon samples. It is shown that four different defect states are identified at the Si–SiNx interface. Energy-dependent electron and hole capture cross sections were also measured by small-pulse DLTS. Samples with plasma NH3 pretreatment and RTA show the lowest DLTS signals, which suggest the lowest overall interface states density. Moreover, SiNx with RTA passivates interface states more efficiently in n-type Si compared with p-type Si; also the deep-level parameters change in n-type Si but not in p-type Si. The combination of plasma NH3 pretreatment and RTA is suggested for application in the solar cell fabrication.
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