No abstract

Since the semiconductor industry hit the 0. 18

Trends in the design feature shrinking that outrun the progress in the lithography technologies require critical efforts in the layout, process, and model development. Printing a layout is no longer a problem only for the lithographers; it has penetrated into the layout stage as well. Layout patterns are getting more aggressive, raising serious printability concerns. This requires very accurate models to analyze the manufacturability issues. This also often requires simultaneous analysis and optimization of both layout and the process. Most advanced layout patterns are extremely hard to manufacture and consequently run into the risk of re-spins. Therefore, an early pre-tapeout analysis and troubleshooting of various layout, process, and RET issues has become a very important task. Our paper gives examples of how these and other related issues can be addressed using a commercially available Design-for-Yield integrated environment.