Dimensions for 32nm generation logic are expected to be ~45nm. Even with high NA scanners, the k 1 factor is below 0.32. Gridded-design-rules (GDR) are a form of restricted design rules (RDR) and have a number of benefits from design through fabrication. The combination of rules and topologies can be verified during logic technology development, much as is done with memories. Topologies which have been preverified can be used to implement random logic functions with "hotspot" prevention that is virtually context-independent. Mask data preparation is simplified with less aggressive OPC, resulting in shorter fracturing, writing, and inspection times. In the wafer fab, photolithography, etch, and CMP are more controllable because of the grating-like patterns. Tela Canvas™ GDR layout was found to give smaller area cells than a conventional 2D layout style. Variability and context independence were also improved.

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In this paper, the simulation of wafer images for Attenuated Phase Shift Masks (ATTPSM) and repaired binary masks are performed by Virtual Stepper® System in a real production environment. In addition, the Automatic Defect Severity Scoring (ADSS) module in Virtual Stepper is also used to calculate the defect severity score for each defect. ADSS provides an overall score that quantifies the impact of a given defect on the surrounding features. For the binary masks, the quality of repaired defects is studied. For the ATTPSM, three types of programmed defects (protrusion, intrusion, and pin-dot) on both line/space and contact hole patterns are assessed. Wafer exposures are performed using 248 nm imaging technology and inspection images generated on a KLA -Tencofs SLF27 system. These images are used by the Virtual Stepper System to simulate wafer images under the specific stepper parameters. The results are compared to SEM images ofresist patterns and Aerial Image Measurement System (AIMSTM) simulated results.