Low k 1 logic design using gridded design rules

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

2012

Abstract-Design rules have been the primary contract between technology developers and designers and are likely to remain so to preserve abstractions and productivity. While current approaches for defining design rules are largely unsystematic and empirical in nature, this paper offers a novel framework for early and systematic evaluation of design rules and layout styles in terms of major layout characteristics of area, manufacturability, and variability. The framework essentially creates a virtual standard-cell library and performs the evaluation based on the virtual layouts. Due to the focus on the exploration of rules at an early stage of technology development, we use first order models of variability and manufacturability (instead of relying on accurate simulation) and layout topology/congestion-based area estimates (instead of explicit and slow layout generation). Such a framework can be used to co-evaluate and co-optimize design rules, patterning technologies, layout methodologies, and library architectures.

Section: Variabilitymentioning

confidence: 99%

DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

2012

“…As a results, option (b) leads to less cornerrounding than option (a). Yet, we assume option (a) in our implementation because it is very regular and, consequently, more favorable for lithography [18,19]. In these structures, gate-pitch is twice the minimum pitch of single patterning, which ensures pitch-doubling, and small notches that appear on vertical lines correspond to contact-landing pads, which are avoidable in processes in some processes (e.g.…”

Section: Layout Restrictions At Poly-line Layermentioning

confidence: 99%

Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control

Torres

IEEE Trans. Semicond. Manufact.

2011

Abstract-1 We propose shift-trim double patterning lithography (ST-DPL), a cost-effective double patterning technique for achieving pitch relaxation with a single photomask. The mask is re-used for the second exposure by applying a translational mask-shift. An additional non-critical trim exposure is applied to remove extra printed features. ST-DPL can be used to pattern critical layers and is very suitable for regular and gridded layouts, where redesign effort and area overhead are minimal. In this paper, the viability of ST-DPL is demonstrated through a design implementation at the poly and contacts layers in bidirectional layouts. Standard-cell layouts are constructed so as to avoid layout decomposition conflicts, which are found to be the limiting factor for the pitch relaxation that can be achieved with double-patterning (ST-DPL as well as standard DPL). 2× pitch relaxation being associated with a considerable area overhead, 1.8× pitch relaxation is achieved in our implementation while ensuring no layout decomposition conflicts and a small area overhead. Specifically, in comparison to layouts assumed to be feasible with a hypothetical single-patterning process, we observe virtually no area overhead when ST-DPL is applied to the poly layer (<0.3% cell-area overhead) and no more than 4.7% cellarea overhead when ST-DPL is applied at both the poly and contacts layers. The proposed method has many benefits over standard pitch-split double-patterning: (1) cuts mask-cost to nearly half, (2) reduces overlay errors between the two patterns, (3) alleviates the bimodal line-width distribution problem in double patterning, and (4) slightly enhances the throughput of critical-layer scanners.

“…In our framework, CDU is described by a distribution, which captures the dependency on dose and focus variations. Pattern-dependency is captured by using different CDU 3σ values for each poly-patterning style including 1D/2D patterning and fixed/non-fixed pitch, which can seriously impact CDU [11,35,36].…”

Section: Variabilitymentioning

confidence: 99%

A framework for early and systematic evaluation of design rules

Proceedings of the 2009 International Conference on Computer-Aided Design

2009

Abstract-Design rules have been the primary contract between technology and design and are likely to remain so to preserve abstractions and productivity. While current approaches for defining design rules are largely unsystematic and empirical in nature, this paper offers a novel framework for early and systematic evaluation of design rules and layout styles in terms of major layout characteristics of area, manufacturability, and variability. Due to the focus on co-exploration in early stages of technology development, we use first order models of variability and manufacturability (instead of relying on accurate simulation) and layout topology/congestion-based area estimates (instead of explicit and slow layout generation). The framework is used to efficiently co-evaluate several debatable rules (evaluation for a 104-cell library takes 20 minutes). Results show that: a) diffusionrounding mainly from diffusion power-straps is a dominant source of variability, b) cell-area overhead of fixed gate-pitch implementation compared to 1D-poly implementation is tolerable (5%) given the improvement in variability, and c) 1D-poly restriction, which improves manufacturability and variability, has almost no area overhead compared to 2D-poly. In addition, we explore gate-spacing rules using our evaluation framework. This exploration yields almost identical values as those of a commercial 65nm process, which serves as a validation for our approach.