No abstract

The photosensitive organic passivation for the conventional back channel etched (BCE) thin film transistors (TFTs) has been investigated. Through the organic material, the TFT array fabrication process steps can be reduced and higher aperture ratio can be achieved for higher LCD panel performance. The interface between the organic passivation layer and the back channel of the amorphous active region has been passivated by the plasma treatment and the devices exhibit lower leakage current than the conventional silicon nitride (SiN x ) passivation layer of BCE TFTs. The leakage currents between Indium-tin oxide (ITO) pixels and the TFT devices, as well as the thermal-humidity reliability tests have also been investigated in this paper.

Two types of dual-gate a-Si:H TFTs were made with transparent indium-tin-oxide (ITO) top-gate electrodes of different lengths to investigate the static characteristics of these devices. By changing the length of the ITO top gate, we found that the variations in the on-currents of these dualgate TFTs with dual-gate driving are due to the high resistance of the parasitic intrinsic a-Si:H regions between the back electron channel and the source/drain contact. In the off-state of the dual-gate-driven TFTs, the Poole-Frenkel effect is also enhanced due to back-channel hole accumulation in the vicinity of the source/drain contact. Furthermore, we observed for the first time that under illumination the dual-gate-driven a-Si:H TFTs exhibit extremely low photo-leakage currents, much lower than that of single-gate-driven TFTs in a certain range (reverse subthreshold region) of negative gate voltages. The high on/off current ratio under backside illumination makes dual-gate TFTs suitable devices for use as switching elements in liquid-crystal displays (LCDs) or for other applications.

We introduce a novel self‐aligned etch stopper, sidewall‐contact a‐Si:H TFT (ESSC‐TFT) which allow us to reduce the photo leakage current by the island‐in structure. This ESSC‐TFT design reduces the volume of a‐Si film, the active region can totally be shielded by the gate metal resulting in the prevention from direct back light illumination. With the sidewall‐contact, the hole current is reduced due to the smaller contact area, and we expect the source, drain parasitic intrinsic resistance of a‐Si can be also lessened by the ESSC‐TFT structure. Although the defects between etched a‐Si and n+ a‐Si film may degrade the on current, the ESSC‐TFT still exhibits higher on‐off ratio than the one in traditional ES‐TFT structure.