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We describe a liner' for Cu-Damascene multilevcl ULSI interconnects, which satisfies all the important requirements for a high performance and reliable Cu interconnect technology. This liner is implemented in the first manufacturing process to produce and ship CMOS chips with Cu interconnects'. The liner is a bilayer from a family of hcp/bcc-TaN followed by bcc-Ta (a-Ta), deposited sequentially in a single PVD chamber from a pure Ta target, using Ar and Nz sputtering gases. This bilayer simultaneously maximizes adhesion to the interlevel dielectric and the Cu fill, and has very low in-plane resistivity (-30-60 M-cm, depending on TaN/Ta thicknesses). These qualities produce high-yield, highly reliable, and electromigration-redundant Cu interconnects. Introduction Many liners have been implemented in experimental Cu integration schemes. The family of Ta-based compounds has emerged prominently. Ta (P-phase) was first shown to be an excellent Cu diffusion barrier in 1986 by Hu et d 3 . It was since found4 that a low background level (e.g. < l o 7 Torr) of O2 or H 2 0 was responsible for decreasing Cu diffusivity through Ta grain boundaries. (Presumably, current studies that fmd reduced Ta barrier performance stem fiom the low base pressures of modem PVD systems, and could be helped by a controlled leak of 02.) Such a P-Ta(0) barrier was used in the first multilevel Cu integration in polyimide ILD', due to its optimal adhesion to the materials used6. For dualDamascene integration in Si022 however (see fig. 1 .), Ta and Ta2N7 lack adequate adhesion to SO2, whereas TaN/SiO2 adhesion is excellent ( fig. 2). On the other hand, Cu/TaN adhesion is relatively poor. In fact, the liner/ILD and Cdliner adhesion have conflicting dependencies on N% in TaN,. We believe it is essential to maximize adhesion at all interfaces, especially the Cu/liner one. This is both to resist delamination during processing or thermal stressing, and for electromigration resistance in fine Cu lines, where interfacial and surface migration play a large role*. As confirmed elsewhere', Cu E-M lifetimes are lower when against a TaN vs. a Ta liner. Unlike CdTaN, /W, and /TiN, the CdTa interface exhibits high wetting" and atomic-scale mixing". This occurs without alloying, which would consume Cu atoms. The Cu/Ta interface is thus uniquely optimal among the commonly studied candidates.Another essential liner quality which has not been addressed generally elsewhere and which is lacking in TaN or TiN, is the capacity for current-strapping (electromigration rcdundancy) by a suitably thin liner. In thc event of Cu defects or elcctromigration wearout, a propcr liner should prevent or dclay open-circuit failurc, cvcn at maximum rated currcnt concentrated in the liner. Such rcdundancy is achieved by the TiAh alloy ovedunder cladding in our AI(Cu) interconnects, and is a reliability requirement for our Cu interconnccts as well. DiscussiodData Our evaluation factors for designing a Cu Damascenc liner are shown in Table I, with results from screening of many candidat...

Significant progress has been made in building multilevel copper interconnection systems for advanced microelectronics. In this article, we examine some of the materials science issues underlying this progress, and indicate where significant materials challenges remain. It is probable that several approaches to process integration will be developed for copper interconnections, as has been the case with aluminum systems. The first successful demonstration of a fully integrated 4-level copper/polyimide (Cu/PI) interconnection system has been described by Luther et al. of IBM. A schematic cross section of this interconnection system is shown in Figure 1, indicating multiple layers of BPDA-PDA polyimide (PI 5810), Cu lines and studs, and layers of Ta and Si3N4 which serve as diffusion barriers, adhesion layers, and stopping layers in the patterning and planarization processes. This system demonstrates excellent planarity, as shown in the SEM cross section in Figure 2. The electromigration lifetime of this Cu/PI system is greatly improved relative to state-of-the-art aluminum-based systems, and the dielectric integrity appears adequate. Signal propagation studies also confirm the performance improvements anticipated for copper as a low-resistivity conductor and the use of Cu may allow significant capacitance reduction (≃ 25%) simply by scaling Cu lines to equal the resistance of Al lines. In parallel with efforts to introduce Cu metallization for its low resistivity, extensive efforts are under way to replace SiO2 with lower dielectric constant insulators.