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The Gate All Around (GAA) MOSFET is considered as one of the most promising devices for downscaling below 50 nm. By surrounding the channel completely, the gate gains increased electrostatic control of the channel and short-channel-effects (SCEs) can be drastically suppressed. However, challenges still remain to resolve the important issues particularly concerning hot-carrier reliability and accurate device models for nanoscale circuit designs. Hot-carrier effects have been the major issues in the longterm stability of subthreshold performances in a nanoscale MOS transistor. In this paper we present a two-dimensional analytical analysis of the subthreshold behavior, subthreshold current and subthreshold swing, including the interfacial hot-carrier effects. The calculated results of the proposed approach match well with those of the 2-D numerical device simulator. The present work provides valuable design insights in the performance of nanoscale CMOS-based devices including hot-carrier degradation effects.

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