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Abstract-A new nonlinear, charge-conservative, scalable, dynamic electro-thermal compact model for LDMOS RF power transistors is described in this paper. The transistor is characterized using pulsed I-V and S-parameter measurements, to ensure isothermal conditions. A new extrinsic network and extrinsic parameter extraction methodology is developed for high power RF LDMOS transistor modeling, using manifold de-embedding by electromagnetic simulation, and optimization of the extrinsic network parameter values over a broad frequency range. The intrinsic model comprises controlled charge and current sources that have been implemented using artificial neural networks (ANNs), designed to permit accurate extrapolation of the transistor's performance outside of the measured data domain. A thermal sub-circuit is coupled to the nonlinear model. Largesignal validation of this new model shows a very good agreement with measurements at 2.14 GHz.

Abstract-A new extrinsic network and extrinsic parameter extraction methodology is developed for high power RF LDMOS transistor modeling. This new method uses accurate manifold deembedding using electromagnetic simulation, and optimization of the extrinsic network parameter values over a broad frequency range. The new extrinsic network accommodates feedback effects which are observed in high power transistors. This improved methodology allows us to achieve a good agreement between measured and modeled S-parameters in the frequency range of 0.5 to 6 GHz for different bias conditions. Large-signal verification of this new model shows a very good match with measurements at 2.14 GHz.

Abstract-In this paper, we present a multi-physics approach for the simulation of high-power RF and microwave transistors, in which electromagnetic, thermal, and nonlinear transistor models are linked together within a harmonic-balance circuit simulator. This approach is used to analyze a laterally diffused metal-oxide semiconductor (LDMOS) transistor that has a total gate width of 102 mm and operates at 2.14 GHz. The transistor die is placed in a metal-ceramic package, with bondwire arrays connecting the die to the package leads. The effects of three different gate bondpad layouts on the transistor efficiency are studied. Through plots of the spatial distributions of the drain efficiency and the time-domain currents and voltages across the die, we reveal for the first time unique interactions between the electromagnetic effects of the layout and the microwave behaviour of the large-die LDMOS power field-effect transistor (FET).Index Terms-Global modeling, electrothermal, laterallydiffused metal-oxide-semiconductor (LDMOS) transistor, power field-effect transistor (FET).

This paper presents a rigorous method for low impedance loadpull measurements using a 6-section Tschebyscheff transforming water-cooled pre-matching test fixture. The transformers were designed to be able to accurately determine S-parameters that represent each fixture half at the fundamental frequency of operation f o and its second and third harmonics, 2f o and 3f o . A twotier non-50 Ω TRL calibration technique was used to establish the measurement reference planes. In order to accurately establish the calibrated system impedance, a simulated Time Domain Reflectometry (TDR) technique was employed. The calibration of the loadpull system was confirmed by calculating the difference between the measured and calculated transducer gain (∆Gt). This difference provides a measure of the measurement uncertainty. The largest uncertainty, in areas of interest on the Smith chart, was found to be 0.25 dB. The fixture was successfully utilized to measure the loadpull performance of one of Motorola's LDMOS, 90 Watt, 1.9 GHz high power transistors.