Borophosphosilicate glass (BPSG) has been widely used as a premetal dielectric for planarization of high aspect ratio (AR) topography in advanced very large scale integrated device fabrication 1-3 due to its reflow capability at elevated temperatures. High temperature annealing is used to eliminate as-deposited voids and stabilize the BPSG layer. However, as device dimensions shrink, the allowable thermal cycle for BPSG deposition and reflow is being reduced. For straight or even reentrant trench wall profiles, other processes with good conformality, e.g., undoped silicon oxide and phosphosilicate glass, are not suitable to achieve void-free gap fill at a >5:1 aspect ratio with uniform etch resistance inside the gap. Even though the conformality of the as-deposited BPSG films has been greatly enhanced by using O 3 /tetraethoxysilane (TEOS) chemistry 4-5 instead of the conventional O 2 /silane or plasma enhanced processes, it remains a challenge to deposit enough material down into the small size gaps to achieve the best reflow at minimal annealing temperature. In this paper, we present some characterization results on an subatmospheric pressure chemical vapor deposition (SACVD) BPSG process to extend gap filling capability. Based on this information, a two-step deposition process was developed, which is capable of achieving void-free gap filling at 0.06 m trench width and a >6:1 aspect ratio even with reentrant sidewall profile.Experimental The experiments were conducted in an Applied Materials GigaFill SACVD Centura ® chamber, which is described in detail elsewhere. 6 The schematic is shown in Fig. 1, briefly, this is a single wafer process tool equipped with a high temperature heater and remote plasma clean system. Liquid TEOS and dopants (triethylborate, TEB and triethylphosphate, TEPO) are vaporized via PLIS (precision-liquid-injection-system) and carried into the process chamber using He 7 as a carrier gas, then mixed with O 3 . After flow distribution, the gas mixture impinges onto the wafer, which is placed on the hot heater surface, to form a BPSG film. After each wafer deposition, a chamber cleaning process is performed using fluorine atoms generated by the remote plasma clean system to remove any residue buildup during deposition and ensure process repeatability from wafer to wafer. The process controlling variables include chamber pressure (P), heater temperature (T s ), TEOS and dopant (TEB and TEPO) flow rates, O 3 concentration, and flow rate.Most of the film properties were measured on a bare silicon substrate, whereas the gap filling performance is evaluated on patterned structures. The postdeposition annealing was performed either in a furnace or in the Applied Materials rapid thermal processing (RTP) Centura system. The scanning electron micrograph photos were taken after sample decoration using a 6:1 buffer oxide etch for 10 s.Results and Discussion A statistical design of experiments (DOE) was employed to characterize the SACVD BPSG process. A screening experiment was designed to evaluate both...