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In the past decade wafer level packaging (WLP) has been proven to be a very competitive solution regarding performance, miniaturization and costs for a wide range of applications. However, they are up to now not matching the performance of hermetically sealed Glass or Glass-to-MetalSeal packages, esp. when considering application in extreme environment. In this paper a novel packaging technology is proposed, allowing hermetic passivation and encapsulation of microelectronic devices on wafer-level. This technology combines the unique properties of microstructuring of glass on silicon process [1] with the capabilities of a wafer-level packaging technology using Silicon-Via-Contacts [2]. This new processing technology is enabling hermetic encapsulation of devices on wafer-level comprising an unique, cost effective passivation process performed at temperatures below 120°C. Wafer-Level-Packaging and Redistribution using PolymerMost of the successful wafer-level-packaging technologies introduced in the past [3,4] are using polymers as dielectric material for the passivation of microelectronic elements as well as electrical insulation of the device and the redistribution leads of the package. A broad class of materials have been developed ranging from epoxy-based materials and spin-on polymers to polyimids and BCB.Acceptable microstructuring results can be achieved with those materials by plasma etching using a photo-resist mask or by choosing a class of intrinsic photosensitive passivation polymers applying lithography directly.Generally the polymer passivation has to be cured after application to the wafer. The degree of cure of that passivation materials has a strong impact on their passivation properties and therefore on the overall reliability of the packaged electronic devices. If thermal curing is applied, Tg of the polymers is systematically lower than the bake temperature. Standard curing conditions are in the range of 160°C to 380°C for several minutes to hours depending on the polymer material. Sensitive electronic devices i.e. CMOS or analog IC's may suffer significant loss of device performance when exposed to those curing conditions.

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The novel wafer-level packaging (WLP) process described in this paper allows quasi-hermetic capping of optical devices on wafer-level yielding miniaturized glass cavity windows on top of the optical area, at the same time leaving the contact area accessible for standard electrical connections i.e. wire bond. These smaller chip-size optical cavity packages are used within standard chip-on-board (COB) assemblies for high performance optical applications providing high yield and utmost reliability.In this paper the process flow of generating optical cavity glass wafers as well as of the wafer-level capping process is demonstrated and reliability data on wafer-level and packagelevel are discussed. Fig. 1: Smaller chip size glass cavity window on product wafer I. Wafer-Level Capping of Optical DevicesWafer level packaging of optical devices is becoming more and more mainstream [1]. Beside the overall deciding advantages of cost per die and system yield, performance and reliability targets can be matched for an increasing range of applications.In this paper we disclose the general manufacturing process for capping of devices on wafer level using a microstructured cap wafer. The process yields the uniqueness to bond the caps only on top of the selected areas leaving the exclude areas untouched e.g. for wire bond. This provides an ideal compromise between WLP and classical COB with the advantage that sensitive optical structures are selectively sealed on wafer-level in a very early stage -significantly reducing yield loss due to particle contamination especially well-known for image sensor modules [2]. Furthermore the proposed process provides an increased flexibility for assembly in order to bring costs down.Depending on the method of micro structuring of the cap wafer, the individual caps may provide a cavity for the encapsulated devices. These cavities being obvious and well-known for MEMS are also required for optical applications like MOEMS or image sensors -e.g. if these have micro lenses on the optical area of a camera chip. However, for optical chips the cavity, the glass cap and their relevant surfaces in particular, are contributing to the overall optical performance of the device. Therefore their tolerances and quality have to meet stringent optical requirements. Fig. 2: Typical glass cavity window after dicing bonded to a dummy wafer. An 80 um glass rim acts as the bond frame with a total width of 100 um. In order to achieve these tight design rules the amount of the bond adhesive as well as its bleeding during the bonding process must be well controlled.As an example the wafer level package of miniaturized photodiodes used for high density optical storage (HD-DVDas shown in Fig. 1) is discussed, demanding special attention on advanced optical performance, UV stability and high reliability. Since intensive blue laser light (405 nm) is used, a glass window package is considered to perfectly meet the needs for long term stability and performance. Having the devices protected very early in the assembly process, ...