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Logic State Imaging (LSI) using Infra-Red Emission Microscopy (IREM) [1-4] has been an indispensable technology for silicon CMOS process development and product debug applications. Its main limitations are relatively poor spatial resolution due to the broadband near-infrared photons emitted, and poor Signal to Noise Ratio (SNR) with low voltage and low leakage processes and products. Continuous-Wave Laser Scanning Microscope (CW-LSM) based Signal Imaging and Probing (CW-SIP) [5-9] technology is also widely used. It features inherently better spatial resolution than IREM, due to the use of monochromatic 1319nm or 1064nm laser light, and high SNR due to its weaker dependence on voltage and leakage, and, for signal imaging applications, the use of narrow band detection to reduce noise. However, CW-SIP can only detect modulating signals, so it couldn’t previously be applied to LSI. In this paper, we introduce an innovative approach that overcomes this limitation to enable Laser Logic State Imaging (LLSI). Actual fault isolation and design debug cases using this technology are presented to show its advantages in terms of resolution (>50% better), SNR (>2X better) and throughput time improvement, especially at low voltages (down to 500mV).

A post-silicon design validation methodology using on-die clock design for debug (DFD) circuits working together with advanced optical silicon probing techniques has been developed. Innovations are on increasing the nodal observability by using an infrared photon-emission (IREM) logic state image (LSI) technique and on increasing the nodal controllability by using a laser assisted device alternation (LADA) technique. This new approach provides a better solution for determining the root causes of marginal circuits associated with process variations or logic cones across multiple clock, voltage, and/or temperature operation domains.

Pre-silicon power modeling, post-silicon power validation, and power debugs design efforts have significantly increased to meet speed performance, reliability deliverables and design robustness for manufacturing. IREM based power debug flow has been developed to isolate marginal circuits with excessive static and dynamic power consumption. Three root cause analysis cases are presented to demonstrate the success of this novel post-silicon debug flow.

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