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2nd generation lGbit 2GHz Embedded DRAM (eDRAM) with 4X lower self refresh power compared to prior generation is developed in 22nm Tri-Gate CMOS technology. Retention time has been improved by 3X (300us@95°C) by process and design optimizations. Source synchronous clocking is integrated in the design to reduce clock power without penalizing bandwidth.Charge pump power is reduced by 4X by employing comparator based regulation. Temperature controlled refresh enables minimum refresh power at all temperature conditions.

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Pre-silicon power modeling, post-silicon power validation, and power debugs design efforts have significantly increased to meet speed performance, reliability deliverables and design robustness for manufacturing. IREM based power debug flow has been developed to isolate marginal circuits with excessive static and dynamic power consumption. Three root cause analysis cases are presented to demonstrate the success of this novel post-silicon debug flow.

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