No abstract

Spike Rapid Thermal Annealing (RTA) is commonly used method for source and drain dopant activation in 65nm CMOS technology. It is found that the Idsat variation is very sensitive to RTA temperature. To better control the Idsat uniformity across the shot, a systematic study on STI and poly pattern density distribution across the shot field and their effects on the RTA temperature was carried out. It was demonstrated that the STI and poly pattern density variation across the field will result in more than 10ºC RTA temperature variation. To minimize the effect, an optimization of RTA ramp rate and peak temperature was studied. Source/drain (S/D) extension and S/D implant optimization has also been done for the reduction of PMOS device Idsat temperature sensitivity

Three key process steps in shallow trench isolation (STI) technology: STI liner oxide, STI to AA step height, and annealing temperature. Their impacts on NMOS devices leakage, SRAM standby current and Vccmin have been studied. MOSFET transistors off state current (Ioff) and body current (IB) were measured at varied length of diffusion (LOD) for STI stress effect analysis. For low power NMOSFET transistors, IB is seen to be the main part of Ioff and has a strong correlation to the processes that modulates STI stress. The experiment results show that the STI stress level can be much reduced by decreasing STI oxide RTA temperature and liner ox thickness, hence leading to lower IB and SRAM standby current. It is also demonstrated that SRAM Vccmin can be improved ~10% by STI stress reduction.

GOI (Gate Oxide Integrity) improvement in 65nm SAC OX (Sacrificial Oxide) free process integration was studied in this paper. After studying the effects of various processes in STI (Shallow Trench Isolation) module with SAC OX free scheme on GOI, it was found that the dominant process that could degrade GOI was the STI HDP (High Density Plasma) gap fill process. STI HDP gap fill process could cause Si damage on AA corners, also named as AA clipping, which will result in irregular corners and hence a thinner gate oxide formation at imperfect AA corners. This was observed by a TEM (transmission electron microscopy) study. In SAC OX free scheme, the exposed AA Si corners that were damaged during the HDP process did not get consumed and repaired while they would have gotten in the scheme with SAC OX and hence degraded GOI. By optimizing the STI gap fill processes and hardware configuration, the AA clipping can be greatly reduced and GOI can be improved to the required level.