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It is shown in the study that Arsenic improves 30% device Idsat variation compared to Ph implantation. SRAM Vccmin value may be improved around 4% too. While it is found that, compared to Ph implantation, Arsenic critically increases junction leakage current, which may account for more than half part of the total off current for high threshold voltage (Vth) device with gate length less than 50nm. The large junction leakage current also leads to 5% device performance degradation and SRAM stand by leakage current (Istby) 15% increasing. Device reliability study exhibits that PMOS negative bias temperature instability (NBTI) performance is deteriorated by Arsenic implantation.

Spike Rapid Thermal Annealing (RTA) is commonly used method for source and drain dopant activation in 65nm CMOS technology. It is found that the Idsat variation is very sensitive to RTA temperature. To better control the Idsat uniformity across the shot, a systematic study on STI and poly pattern density distribution across the shot field and their effects on the RTA temperature was carried out. It was demonstrated that the STI and poly pattern density variation across the field will result in more than 10ºC RTA temperature variation. To minimize the effect, an optimization of RTA ramp rate and peak temperature was studied. Source/drain (S/D) extension and S/D implant optimization has also been done for the reduction of PMOS device Idsat temperature sensitivity