The upcoming 45nm device node is a point at which newer field-based (i.e., dense pixel-based) OPC simulation methods may begin to show advantages over sparse-sampling ("flash") simulation methods. Field-based simulation provides computational efficiencies in applications where a large number of model evaluation locations are needed, and where the simulated layout geometry is complex. Field-based simulation leverages computation in the frequency domain, whereas sparse-sampling methods operate in the space domain. Mathematically, both methods are equivalent but their respective numerical methods give rise to some implementation differences for OPC applications. These differences include different optimization strategies for hierarchical processing, and fine-grained feature symmetry control for critical matched-transistor circuits (such as SRAM, where noise margin is a fundamental device control issue). An optimum, field-based OPC solution will address these differences without compromising the performance benefits of field-based methods. In this paper we describe and compare the manufacturing implementation of flash-based and field-based OPC at the 45nm and 32nm device nodes.
In advanced semiconductor memory manufacturing, the feature size keeps aggressively shrinking, creating problems in the fabrication process and leading to decreasing yield. Three key factors that can impact memory process and yield are lithographic process window, full field CD uniformity (CDU), and correction run time performance. In this paper, we describe and present a mask processing technique utilizing a) global array detect (GAD) for detecting and optimizing cell repetition, b) periodic boundary condition (PBC) for preserving simulation and mask symmetry, and c) cell-level ILT (CLILT) flow to process repeated cell regions and blend various design parts. With GAD + PBC + CL-ILT processing, we can achieve a perfectly consistent mask array region with enlarged process window and minimum local CD variation for a full field mask. Moreover, with fewer pattern units (called templates) to process, we can complete full chip ILT with reasonable time and compute resources compared to OPC full chip correction. In this paper, we show simulation and wafer print results including pattern fidelity, process window, mask consistency, and run time data.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.