This paper presents a new transformation for the scheduling of memory-access operations in High-Level Synthesis. This transformation is suited to memory-intensive applications with synthesized designs containing a secondary store accessed by explicit instructions. Such memory-intensive behaviors are commonly observed in video compression, image convolution, hydrodynamics and mechatronics. Our transformation removes load and store instructions which become redundant or unnecessary during the transformation of loops. The advantage of this reduction is the decrease of secondary memory bandwidth demands. This technique is implemented in our Percolation-Based Scheduler which we used to conduct experiments on a suite of memory-intensive benchmarks. Our results demonstrate a signicant reduction in the number of memory operations and an increase in performance on these benchmarks.

One of the challenging tasks in codegeneration for embedded systems is reg ister assignment. When more live variables than registers exist, some variables willnecessarilybeaccessedfrom data memory. Because loops are typicallyexe cuted many times and are often time-critical, good registerassignment in loops is exceedingly important as accessing data memory can degrade performance. The issue offinding an optimal register assignment to loops has been openfor some time. In this paper, we present a techniquefor optimal (i.e., spill mini mizing) register assignment to loops. First, we present a technique for register assignment to processor cores which are characterized by a consolidated regis ter file. Then, we extend the technique to include architecture styles which are characterized by the partitioning of registers into multiple register files and/or a combination of general-and special-purpose registers. Experimental results demonstrate that, while the optimal algorithm may be computationally pro hibitive, heuristic versions obtain results with performance better than that of an existing graph coloring approach.

SUMMARYThe efficient execution of Java programs presents a challenge to hardware and software designers alike. The difficulty, however, lies with the Java bytecodes. Their model of a simplistic, platform-independent stack machine is well-suited for portability, though at the expense of execution speed. Various approaches are being proposed to increase the speed of Java bytecode programs, including: (i) on-the-fly compilation to native code (also known as JIT or 'just-in-time' compilation); (ii) traditional ('ahead-of-time') compilation of bytecodes to some higher-level intermediate form and then to native code; and (iii) translation of bytecodes to a higher-level language and then use of an existing compiler to produce native code. Speedups of the order of 50 over standard bytecode interpretation have been claimed.All of these approaches rely upon bytecode analysis (of varying sophistication) to extract information about the program, which is then used to optimize the native code during the translation process. However, extracting information from a lower-level representation such as the Java bytecodes can be very expensive. Also, given the fact that most approaches for executing Java bytecodes cannot spend a great deal of time recovering high-level information, the solutions adopted during the translation process must use faster and less accurate analysis techniques, thus penalizing the quality of the native code.In this paper we propose an optimization approach based on bytecode annotations. The bytecodes are annotated during the original source code to bytecode translation, allowing both traditional interpretation by a JVM and aggressive optimization by an annotation-aware bytecode compiler. Annotations hinder neither portability nor compatibility, while preserving optimization information that is expensive to recompute. Preliminary results yield bytecode with C-like performance using JIT technology.

The ecient execution of Java programs present s a c hallenge to hardware and software designers alike.The diculty h o wever lies with the Java b ytecodes. Their model of a simplistic, platform-independent stack machine is well-suited for portability, though at the expense of execution speed. Various approaches are being proposed to increase the speed of Java b ytecode programs, including: (1) on-the-y compilation to native code (also known as JIT or \just-in-time" compilation); ( 2) traditional (\ahead-of-time") compilation of bytecodes to some higher-level intermediate form and then to native code; and (3) translation of bytecodes to a higher-level language and then use of an existing compiler to produce native c o d e .Speedups on the order of 50 over standard bytecode interpretation have been claimed.All of these approaches rely upon bytecode analysis (of varying sophistication) to extract information

Multiple instruction issue processors place high demands on register file bandwidth. One solution to reduce this bottleneck is the use of multiple register files. Register allocation for these architectures then becomes exceedingly important as spill code increases memory bandwidth demands and decreases performance, especially within loops. Previously, we have addressed the issue of finding an optimal allocation of variables to registers within loops for a consolidated register file model. In this paper, we extend that work t o architectures where the available registers have been partitioned into multiple banks. Experimental results demonstrate that, while the optimal algorithm may be computationally prohibitive, heuristic versions obtain acceptable performances.