Optimal register assignment to loops for embedded code generation

Abstract

One of the challenging tasks in codegeneration for embedded systems is reg ister assignment. When more live variables than registers exist, some variables willnecessarilybeaccessedfrom data memory. Because loops are typicallyexe cuted many times and are often time-critical, good registerassignment in loops is exceedingly important as accessing data memory can degrade performance. The issue offinding an optimal register assignment to loops has been openfor some time. In this paper, we present a techniquefor optimal (i.e., spill mini mizing) register assignment to loops. First, we present a technique for register assignment to processor cores which are characterized by a consolidated regis ter file. Then, we extend the technique to include architecture styles which are characterized by the partitioning of registers into multiple register files and/or a combination of general-and special-purpose registers. Experimental results demonstrate that, while the optimal algorithm may be computationally pro hibitive, heuristic versions obtain results with performance better than that of an existing graph coloring approach.

Software synthesis and code generation for signal processing systems

“…Kolson et al [67] have focused on the problem of code generation for irregular data paths in the context of program loops. While the above techniques deal well with special-purpose registers in basic blocks, the do not take into account the data moves required between different iterations of a loop body.…”

Low energy memory and register allocation using network flow

“…The first value denotes the time when the data variable is defined (the write time) and the second value is the time the data variable is used and not needed anymore (the read time). This lifetime may be broken up into a number of intervals, called split [7] lifetimes, (for example if the data variable is read more than once or the data variable is spilled into memory [7,10]). Assume we have a register file with R registers onchip and a (onchip and/or offchip) memory component allowing memory accesses every c control steps (or c clock cycles).…”

“…This approach applies a network flow technique to solve this problem in polynomial time. Some recent algorithms developed for memory allocation either have not addressed low energy [18,10,12], or are very applicationspecific [16]. The problem of register allocation which minimizes energy dissipated was researched in [8] using a maximum cost flow approach, however memory allocation was not considered.…”

“…In particular for low energy applications, memory modules may be operating at lower frequencies (and lower supply voltages to save energy [3]). Other reasons may also exist for using split lifetimes such as spilling of registers [7,10] or as will be shown in section 6 to minimize number of memory accesses. All of these cases can be supported with our model.…”

“…This objective function is defined using equations (3,6,7,8,9,10) to define the coefficients. The general network flow constraints (defined at the end of the previous section 5.1) do not change, except their defined now over the new network flow graph which has more edges defining split lifetimes.…”