Methods of improving aluminum alloy step coverage, such as high temperature and low power processing, have become well known (1-4). Unfortunately, these methods nearly always have drawbacks such as throughput. The process, therefore, needs to be optimized on a case by case basis. An example is provided in this paper for the case of 0.95 micron contacts (1.20 aspect ratio) starting with double level Ai-0.5% Cu-1.0% Si with TIN birrier under first lcJ mct.l nd pure Ti under second level metal; 30% step coverage deemed acceptable.Another drawback to standard high temperature Al alloy deposition is the problem of random metal voids (5). Methods to alleviate this problem are also discussed. Thus there are 2 distinct types of step coverage issues that must be considered seperately:1) Inherent step coverage 2) Random voids. Optimization of each needs to be performed independently. Fig. 1 shows the unacceptable metal step coverage, 9%, when older style deposition conditions are applied to 0.95 micron contacts. Deposition conditions were at 350 C, 7.0 mtorr, and 6.0 Kw deposition power in a Varian 3290. Fig. 2 shows the very good step coverage, 40%, obtainable at 400 C and 2.4 Kw deposition power with rounding of the contact wall by a 30 minute 875 C furnace anneal prior to metal depositon. The problem is that throughput is 2.5 times slower than at 6.0 Kw and 400C pushes the limits of the deposition machine. A compromise is needed. Fig. 3 shows improvement to 22% with rounding of the contact wall by a 10 sec treatment at 1000 C in an AG 2146 Rapid Thermal Processor (RTP)). In some cases furnace rounding may be preferable to RTP rounding. Figure 4 shows results from a 850 C 30 mm furnace rounding. This results in a retrograde contact with unacceptable step coverage. Increasing the temperature to 875 C still at 30 mm results in acceptable rounding, as shown in Fig 5. Step coverageis 20%, equivalent to RTP rounding, but still not good enough. 90 EXPERIMENTAL STEP COVERAGE OPTIMIZATION

This paper reports on the dramatically enhanced effect rapid thermal anneal (RTA) treatment has on the aluminum (Al) diffusion barrier integrity of reactively sputtered low density titanium nitride (TIN). This low density as sputtered TiN is shown to be superior to high density as sputtered TiN after both films have undergone an identical RTA treatment. The superior integrity of the low density TIN is attributed to enhanced oxygen gettering during RTA treatment at the Ti/TIN interface. This oxygen gettering has been shown to create a titanium oxynitnde (TiON) layer between the Ti and TiN which accounts for the greatly enhanced barrier integrity.Reactively sputtered TiN is commonly used as a contact diffusion barrier for submicron Al talliza1 Because of the high aspect ratio contacts used in the submicron process, the TIN barrier coverage at the bottom of the contact is often greatly reduced.2 This reduced coverage makes the barrier integrity extremely critical for the prevention of Al junction spiking in the submicron process, if conventional (i.e. non-collimating,2'4) sputtering technology is used. Previous reports on TiN barrier enhancement 28 fell into two general categories: 1) barrier enhancement by the manipulation and control of deposition parameters such as substrate temperature 3-4, deposition pressure 2,5, and substrate bias voltage6 to deposit a more densifled (or ciystallized) TiN film, and 2) barrier enhancement through the use of post deposition treatments such as air exposure 7 or RTA 8 prior to Al deposition to block fast diffusion pathways by stuffing the TiN film with oxygen. Many studies have used one of these two approaches to report on TiN barrier enhancement. However, there are few reports that have coupled the effects of controlling the deposition parameters and post deposition treatments to develop an improved TiN difflision barrier. In this study we have investigated the effect process parameters have on the density of reactively sputtered TIN films and, in turn, how the TiN density influences the effect post deposition RTA treatment has on barrier integrity. With the development of this relationship we have proposed a mechanism whereby oxygen gettering at the Ti/TiN interface forms a TiON layer that provIdes for a dramatically enhanced diffi.ision barrier. O-8194-1668-1/941$6.OO SPIE Vol. 2335 / 177 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 06/30/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

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The instability of the electrical properties of semi-insulating GaAs materials has been investigated. The presence of chemical contaminants on the surface of the finished wafers is responsible. Simulated thermal conversion using intentional carbon-ion implantation indicates larger concentrations for the possible contaminants on the surface than that in the bulk. The contribution to instability due to preferential gettering of imperfections from bulk by the implant and annealing process was eliminated using intentional Ar-ion implantation. For the samples which exhibited a change in electrical conduction type, a linear relationship between the thickness of the type-converted surface layer and the square root of heat treatment time was observed. It is proposed that the causes for the instability are governed by conventional diffusion mechanisms with multiple electrically active species involved. A positive correlation was also observed between thermally induced electrical instability in ion-implanted material and a reduction in activation, peak carrier density, and Han mobility.

A novel plasma enhanced CVD TiN process was integrated with high density plasma sputter etch preclean (PCII) and 1:1.5 collimated PVD Ti (c-PVD Ti) process to deposit a Ti/TiN liner for tungsten contact and via plugs. The integrated liner process was optimized for a 0.35 μm nonsalicide CMOS device application. RF power and sputter depth used for contact preclean were the major process variants affecting the contact resistance, junction leakage and transistor threshold voltage. Low contact resistance was obtained for a c-PVD Ti thickness of ∼375 Å. Via resistance was significantly lower with c-PVD Ti/CVD TiN liner as compared to only a TiN liner. Contact resistance for c-PVD Ti/c-PVD TiN and c-PVD Ti/CVD TiN liners were comparable while contacts with conventional PVD Ti/TiN liner showed significantly higher values due to poor step coverage. Low junction leakage current was obtained for integrated c- PVD Ti/CVD TiN stack.