We describe an all-optical lithography process that can be used to make electrical contact to atomic-precision donor devices made in silicon using scanning tunneling microscopy (STM). This is accomplished by implementing a cleaning procedure in the STM that allows the integration of metal alignment marks and ion-implanted contacts at the wafer level. Low-temperature transport measurements of a patterned device establish the viability of the process.Keywords: Methods of micro-and nanofabrication and processingThe ability to fabricate devices with atomic precision holds promise for revealing the key physics underlying everything from quantum bits 1,2 to ultra-scaled digital circuits 3-7 . A common atomic-precision fabrication (APFab) pathway uses a scanning tunneling microscope (STM) to create lithographic patterns on a hydrogenpassivated Si(100) surface 8 . Phosphine gas introduced into the vacuum system selectively adsorbs on sites where Si dangling bonds have been re-exposed by patterning 9 , yielding atomically precise, planar structures made of P donors. Unlike electron beam lithography (EBL), which can pattern hydrogen with a resolution of around 100 nm and is unable to image the pattern 10 , the STM is an ideal instrument for this process because it can both pattern and image the hydrogen resist with atomic precision 11 . However, STMs are typically capable of patterning devices only up to 10 µm by 10 µm in size, which are too small to directly contact. A post-patterning microfabrication process, consisting of etching via holes in an encapsulating Si overlayer and then depositing metal in direct contact with the planar donor layer, is used to make electrical contact to the devices. Even the largest features made with the STM are small enough that this contacting process relies on EBL for patterning and 200 nm-scale processing. At this scale, making good electrical contact between a deposited metal and an atomically-thin onedimensional line of donors at the edge of an etched hole is challenging, and even successful EBL process flows in this application are rate-limiting.In this paper, we detail an all-optical lithography contacting process that reduces the time of fabricating an atomic-precision device by an order of magnitude. This is made possible by the integration of both ion-implanted contacts and metal alignment marks in the starting material, which bridge the scale between the largest regions accessible by STM and the smallest length scale accessible by low-cost photolithography. Specifically, the ionimplanted contacts neck down to a small enough area that the STM can place the APFab device in direct contact with them, and extend out to a region large enough

High-fidelity single-shot readout of spin qubits requires distinguishing states much faster than the T1 time of the spin state. One approach to improving readout fidelity and bandwidth (BW) is cryogenic amplification, where the signal from the qubit is amplified before noise sources are introduced and room-temperature amplifiers can operate at lower gain and higher BW. We compare the performance of two cryogenic amplification circuits: a current-biased heterojunction bipolar transistor circuit (CB-HBT), and an AC-coupled HBT circuit (AC-HBT). Both circuits are mounted on the mixing-chamber stage of a dilution refrigerator and are connected to silicon metal oxide semiconductor (Si-MOS) quantum dot devices on a printed circuit board (PCB). The power dissipated by the CB-HBT ranges from 0.1 to 1 μW whereas the power of the AC-HBT ranges from 1 to 20 μW. Referred to the input, the noise spectral density is low for both circuits, in the 15 to 30 fA/ range. The charge sensitivity for the CB-HBT and AC-HBT is 330 μe/ and 400 μe/, respectively. For the single-shot readout performed, less than 10 μs is required for both circuits to achieve bit error rates below 10−3, which is a putative threshold for quantum error correction.

No abstract

Scaling to smaller transistors is increasingly difficult and expensive, necessitating the investigation of alternative fabrication paths that extend to the atomic scale. Atomically precise donor devices can be created using a scanning tunneling microscope (STM). However, these devices are not currently compatible with industry standard fabrication processes. There exists a tradeoff between low thermal budget (LT) processes to limit dopant diffusion and high thermal budget (HT) processes to grow defect-free layers of epitaxial Si and gate oxide. To this end, we have developed an LT epitaxial Si cap and LT deposited Al2O3 gate oxide integrated with an atomically precise single-electron transistor (SET) that we use as an electrometer to characterize the quality of the gate stack. The surface-gated SET exhibits the expected Coulomb blockade behavior. However, the gate's leverage over the SET is limited by defects in the layers above the SET, including interfaces between the Si and oxide, and structural and chemical defects in the Si cap. We propose a more sophisticated gate stack and process flow that is predicted to improve performance in future atomic precision devices.