This brief presents a single-electron injection device for position-based charge qubit structures implemented in 22 nm FD-SOI CMOS. Quantum dots are implemented in local well areas separated by tunnel barriers controlled by gate terminals overlapping with a thin 5 nm undoped silicon film. Interface of the quantum structure with classical electronic circuitry is provided with single-electron transistors that feature doped wells on the classic side. A small 0.7×0.4 µm 2 elementary quantum core is co-located with control circuitry inside the quantum operation cell which is operating at 3.5 K and a 2 GHz clock frequency. With this apparatus, we demonstrate a single electron injection into a quantum dot.Index Terms-Single-electron injection device (SEID), cryogenic circuits, position-based charge qubit, quantum computer, quantum point contact (QPC), quantum operation cell, quantum dot (QD), fully depleted silicon-on-insulator (FD-SOI).

The proliferation of quantum computing technologies has fueled the race to build a practical quantum computer. The spectrum of the innovation is wide and encompasses many aspects of this technology, such as the qubit, control and detection mechanism, cryogenic electronics, and system integration. A few of those emerging technologies are poised for successful monolithic integration of cryogenic electronics with the quantum structure where the qubits reside. In this work, we present a fully integrated Quantum Processor Unit in which the quantum core is co-located with control and detection circuits on the same die in a commercial 22-nm FD-SOI process from GlobalFoundries. The system described in this work comprises a two dimensional (2D) 240 qubits array integrated with 8 detectors and 32 injectors operating at 3 K and inside a two-stage Gifford -McMahon cryo-cooler. The power consumption of each detector and injector is 1 mW and 0.27 mW, respectively. The control sequence is programmed into an on-chip pattern generator that acts as a command and control block for all hardware in the Quantum Processor Unit. Using the aforementioned apparatus, we performed a quantum resonant tunneling experiment on two qubits inside the 2D qubit array. With supporting lab measurements, we demonstrate the feasibility of the proposed architecture in scaling-up the existing quantum core to thousands of qubits.

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This briefpresents two monolithically integrated output-capacitor-less ("caples") low-drop-out (LDO) linear regulators implemented in 22-nm fully depleted silicon-on-insulator (FD-SOI) to support on-die scalable CMOS charge-based quantum processing unit (QPU). The proposed LDOs are used to regulate 0.8 V and 1.5 V input voltages for the programmable capacitive digital-to-analog converter (CDAC) and single-electron detector, respectively. Measured results show that both LDOs can maintain their respective output voltages with a maximum deviation <2% from ∼270 K down to ∼ 3.7 K.