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Miniature, high performance camera modules are found in a range of consumer devices including phones, PDAs, cameras and gaming consoles. According to Gartner the $1B image sensor market will grow to $2.3B by 2013. Image sensor packaging technologies are increasingly required to deliver greater reliability within smaller form factors. Tessera's OptiML™ Micro Via Pad (MVP) wafer-level packaging technology is in production on 200mm wafers. This paper will report on the first joint activity that scales this technology to 300mm. We focus on three critical silicon etches that form the back-bone of the structure. These etches are carried out from the wafer back-side while bonded to a glass carrier. First there is a blanket dry etch. This removes stress introduced by the back-grind. Uniformity control to < ±5% is essential for this process. Second, after a lithography step, tapered silicon trenches are etched forming streets to a certain depth. The trench etch uniformity is critical because it defines the depth range for the subsequent Vias. Profile control is needed to ease the subsequent spray-coat lithography. Lastly, vias are then etched down to metal bond pads on the device side of the wafer. CD and taper control is required here both within wafer and between wafers. End-pointing represents a way of ensuring process reproducibility. In 2010 Tessera carried out 300mm demos with key suppliers. As part of this activity SPTS scaled the above critical silicon etches. The wafers were further processed into functional die. We will describe the etch equipment used, report on the critical processes developed emphasizing the relationships between 200mm and 300mm results and the essential control parameters. We will also demonstrate successful scaling by including data on the electrical performance of packaged devices.

One of the first device types to benefit from TSV implementation is the CMOS image sensor, an image capture device designed to combine high image quality within a compact form-factor that can be mass produced at low cost. End markets include mobile phones, PDAs and gaming consoles. STMicroelectronics is pioneering their production, based on ≤65nm CMOS technology, at its 300mm facility in Crolles. These sensors employ TSVs as part of a wafer level package allowing the camera module to be directly soldered to a phone PCB thereby saving cost, space and time to manufacture. SPTS's Versalis fxP system is being used to combine multiple TSV formation processes onto one platform including hard-mask deposition, hard-mask etching, TSV etching, partial PMD etching, dielectric liner deposition and spacer etching to define the area for the metal contact. All processes are carried out on a silicon wafer bonded to a glass carrier, through which the final device is illuminated. We will present a TSV silicon etch process for 70 μm x 70 μm Vias in a thinned 300mm silicon wafer on glass carriers with an etch rate uniformity of ≤±1% and sidewall scalloping in the range 80–210 nm. We will show that this process can be conveniently mixed in production with the various oxide etches. A PECVD dielectric liner deposited at <200 °C having excellent coverage, thermal stability and adhesion combined with a breakdown voltage >8 MVcm−1 and leakage current <1E-7 Acm−2 will also be described. Process integration aspects will be discussed using high resolution SEMS to show the key material interfaces in critical areas such as feature corners and along sidewalls. Furthermore the successful implementation of TSV technology on ST's CMOS image sensors will be demonstrated through a combination of electrical characteristics, parametric device data and overall device performance/reliability.