Laterally oriented single-crystal silicon nanowires are epitaxially grown between highly doped vertically oriented silicon electrodes in the form of nanobridges. Resistance values extracted from the current-voltage measurements for a large number of nanobridges with varying lengths and diameters are used to propose a model which highlights the relative contribution of the contact resistance to the total resistance for nanowire-based devices. It is shown that the contact resistance depends on the effective conducting cross-section area and hence is influenced by the presence of a surface depletion layer. On the basis of our measured data and constructed model, we estimated the specific contact resistance to be in the range 3.74 x 10(-6) to 5.02 x 10(-6) Omega cm2 for our epitaxial interfacing method. This value is at least an order of magnitude lower than that of any known contact made to nanowires with an evaporated metal film, a common method for integrating semiconductor nanowires in devices and circuits.

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A vast array of new experimental modalities have been enabled in the past several years through the development of pixelated detectors synchronized to probe scanning electronics. Such camera systems can then acquire the rich information present in the central portion of the convergent beam electron diffraction pattern as a function of probe position (4D-STEM). These 4-dimensional (or more) datasets can be readily exploited for phase contrast ptychographic imaging [1], nanoscale strain mapping [2], unit cell resolution quantitative scanning position averaged convergent beam electron diffraction [3], and more. While such detectors are now commercially available from several manufacturers with single electron sensitivity, they are typically limited to approximately 1 millisecond (1 kHz) readout times [4] while conventional integrating-detector HAADF STEM image data is acquired at approximately 10 microsecond (100 kHz) scan rates. This speed constraint places significant limits on accessible fields of view at high resolution due to sample drift, and limits in-situ acquisition to a 4D frame rate of ~1 minute.We present here the development, installation, and characterization of the 4D Camera, a CMOS Active Pixel Sensor that consists of a 576 x 576 array of 10 μm pixels [5] of a design related to the original TEAM detector [6] and an outer HAADF detector with 16 concentric quadrant diodes (Figure 1). Full-frame data from this sensor is read out at 87 kHz, digitized locally at the camera head, and sent over 96 multi-gigabit optical links to 4 Field Programmable Gate Array (FPGA) modules for image assembly, packetization, and routing. In initial tests, the sensor exhibited single electron sensitivity from at accelerating voltages from <30 keV to 300 keV, enabling electron counting methods to effectively eliminate detector readout noise. Initial data has been acquired using a structured mask cut by focused ion beam from a 50nm SiN film coated with 1000 nm of evaporated gold (Figure 2). All data will be streamed in real time via a 400 Gbps 1 km optical link to the Cori supercomputer at the National Energy Research Scientific Computing Center (NERSC), which will perform the 4-dimensional reconstruction and HDF5 file writing before additional asynchronous processing and analysis. By design this is a parallel computational workflow, and NERSC's HPC provides concurrency and a rich software environment to scale up analysis and feedback codes. In-hardware edge-computing on these FPGA devices may also be used to carry out initial data processing (e.g. gain and dark correction, thresholding) before the data is placed on the network.

Abstract-Integrating energy-harvesting photodiodes with logic and exploiting on-die interconnect capacitance for energy storage can enable new, ultraminiaturized wireless systems. Unlike CMOS imager pixels, the proposed photodiode designs utilize p-diffusion fingers and are implemented in a conventional logic process. Also unlike specialized solar cell processes, the designs utilize the on-chip metal interconnect to form a diffraction grating above the p-diffusion fingers which also provides capacitive energy storage. To explore the tradeoffs between optical efficiency and energy storage for integrated photodiodes, an array of photovoltaics with various diffractive storage capacitors was designed in a 90-nm CMOS logic process. The diffractive effects can be exploited to increase the photodiodes' response to off-axis illumination. Transient effects from interfacing the photodiodes with switched-capacitor DC-DC converters were examined, with measurements indicating a 50% reduction in the output voltage ripple due to the diffractive storage capacitance. A quantitative comparison between 90-nm and 0.35-µm CMOS logic processes for energy-harvesting capabilities was carried out. Measurements show an increase in power generation for the newer CMOS technology, however at the cost of reduced output voltage. One potential application for the integrated photodiodes is harvesting energy for a subdermal biomedical device.

Integrating photodiodes with logic and exploiting on-die interconnect capacitance for energy storage can enable new, low-cost energy harvesting wireless systems. To further explore the tradeoffs between optical efficiency and capacitive energy storage for integrated photodiodes, an array of photovoltaics with various diffractive storage capacitors was designed in TSMC's 90 nm CMOS technology. Transient effects from interfacing the photodiodes with switching regulators were examined. A quantitative comparison between 90 nm and 0.35 μm CMOS logic processes for energy harvesting capabilities was carried out. Measurements show an increase in power generation for the newer CMOS technology, however at the cost of reduced output voltage.