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Classical built-in self-test (BIST) architectures are usually relying on linear feedback shift registers (LFSR) for test set generation and test response compaction. This paper is based on extension of the classical BIST, namely hybrid BIST, where pseudorandom test patterns are complemented with precomputed deterministic test patterns to increase the fault coverage and reduce test time. We will propose a method, based on store-and-generate approach, to find the optimal balance between pseudorandom and stored deterministic test patterns. The objective is to minimize the test time at given memory constraints, without losing test quality. We propose an iterative search method and the experimental results on benchmark circuits have proved the efficiency of the proposed approach for hybrid BIST optimization.

A methodology for organization of at-speed functional Built-In Self-Test in processors, based on real functional routines is presented. The proposed self-test includes on-chip test application and response collection by using the functionality of the processor under test. We use divide-and-conquer approach. At component level, tests are targeting faults in components. At processor level, the functionality of the processor is used to apply functional test patterns to each component at-speed.Differently from usual Built-in Self-Test schemes, the test patterns are not needed to store in the chip under test, they will be generated on-line by the resources of the system.

A new teaching concept for teaching testing issues in digital design, which supports the possibility of distance learning as well as a web-based computer-aided teaching is presented. It offers a set of tools ("interactive modules") to inspect the teaching topics and to carry out laboratory research. The interactive modules are focused on easy action and reaction, learning by doing, a game-like use, and fostering students in critical thinking, problem solving skills and creativity.

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