Purpose -The purpose of this paper is to detail progress on the European Commission supported FP7 ASPIS project that is undertaking a multi-faceted approach to develop novel and improved nickel-gold (ENIG) solderable finish chemistries and processes in order to overcome issues such as "black pad" that are known to cause reliability issues. Design/methodology/approach -The ASPIS project has four key and discrete approaches; research into "black pad" formation mechanisms, development of new aqueous chemical deposition methods, formulation of new processes based on ionic liquids and the development of prognostic screening tools to enable early prediction of reliability issues. Findings -Key factors influencing "black pad" formation include immersion gold bath pH value, concentration of citrate and thickness of the immersion gold layer. In addition, copper substrate preparation is also important. Work to develop new metal deposition processes using ionic liquids has also been demonstrated and may provide a viable alternative to more conventional aqueous based chemistries, thereby enabling some of the conditions that lead to "black pad" to be avoided. Research limitations/implications -This paper summarises the work carried out in the first year of a three-year project and so the outputs to date are relatively limited. The project is continuing for another two years, when further progress will be made. It is hoped to report this progress in a future update paper. Originality/value -The ASPIS project has undertaken multiple approaches to the development of new high reliability nickel gold finishes and this combination of approaches should offer synergies over more discrete traditional methodologies. As well as undertaking a detailed analysis of the mechanisms causing reliability problems, radical new formulation and prognostic approaches are also being developed.

No abstract

This article reports on the design of a capacitive pressure sensor fabricated in non-silicon materials. The sensor consists of a thin membrane placed parallel to a rigid reference plane. The membrane and the reference plane act as two electrodes of a capacitor. Deflection of the membrane due to pressure differences results in changes in capacity. These capacity changes are processed to calculate the pressure on the membrane. Several thermo-mechanical performance aspects of the sensor were addressed during the design stage. Promising variants of the sensor were built and subjected to mechanical tests. In addition, numerical techniques were utilized to assess the performance of certain variants before building and testing physical prototypes. The application of this combination of physical experiments and numerical simulations is demonstrated for the selection of a suitable membrane material and membrane dimensions (diameter and thickness), the specification of the substrate thickness in case the sensor is mounted on the backside of an electronics housing, and the selection of a suitable solder interconnect material and interconnect dimensions. A critical aspect in the latter case was the creep behaviour of the solder material, which had to be minimized in order to obtain an acceptable long-term accuracy of the sensor. A sensor membrane and an interconnect design were finally specified on the basis of the outcome of the design studies. It proved to meet the functional demands imposed by the targeted application on a laboratory scale. It will be subjected to reliability and lifetime assessment tests in a next phase.

A novel, cost effective technology to manufacture high density embedded electronic circuitry is demonstrated. The process consists of laser photoablation of the circuitry into a substrate through a mask and subsequent filling using a polymer thick film paste. Because the volume of the substrate is used it is possible to make thick and thereby highly conductive lines using low cost materials and processes. The process is demonstrated for a fan out circuitry in 100 µm thick polyethylene naphthalate (PEN). The fan out circuitry has linewidths of 50 µm and line spacings of 100 µm. The usability of the circuitry is demonstrated by the successful flipchip bonding of a thinned Si daisy chain dummy chip with 176 IO's.

No abstract