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A reliable metal-insulator-metal (MIM) capacitor exceeding 250nF has been integrated into the copper/low-K backend of a high-performance 90nm SOI technology. The reduction of supply grid voltage transients has enhanced microprocessor performance by approximately 10% without increasing the chip area or power consumption.

Thin film properties of LPCVD TiN barriers deposited on Si(100), using TiCl4 and NH3 as reactants, were investigated as a function of deposition temperature between 400 °C and 700 °C. The TiN film chemistry and film composition were studied by AES and RBS techniques, while the microstructural properties (grain size, lattice parameter and texture) were evaluated by XRD. The TiN deposition rates and film resistivities were also determined. Finally the film properties of the TiN barriers as determined by surface analysis were related to the process parameters.

As device geometries continue to scale down, a larger portion of the circuit delay is contributed by interconnects, and the majority of this delay is due to capacitive loading. The replacement of plasma-deposited SiO2 as an intermetal dielectric with an insulator of lower dielectric constant can provide performance improvement through the reduction of capacitance.A commercially available polyimide, BiPhenylene DiAnhydride – Phenylene DiAmine, BPDA-PDA, with an out-of-plane dielectric constant 3.0, is evaluated by integration with AI(Cu) in a double level metal, BiCMOS 4MB SRAM device, with 0.5μm groundrules. Process challenges unique to integration of an organic rather than inorganic insulator are described and experimental features concerning process integration, particularly via etch, Al(Cu) deposition, adhesion and moisture management are presented.

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