Thermoelectric generators, which convert heat directly into electrical power, have great potentialities in the energy harvesting field. The exploitation of these potentialities is limited by the materials currently used, characterized by good thermoelectric properties, but also by several drawbacks. This work presents a silicon-based thermoelectric generator, made of a large collection of heavily p -doped silicon nanostructures. This macroscopic device (area of several mm 2 ) collects together the good thermoelectric features of silicon, in terms of high power factor, and a very reduced thermal conductivity, which resulted in being exceptionally low (1.8 W/(m K), close to the amorphous limit). The generated electrical power density is remarkably high for a Si-based thermoelectric generator, and it is suitable for scavenging applications which can exploit small temperature differences. A full characterization of the device (Seebeck coefficient, thermal conductivity, maximum power output) is reported and discussed.

A large amount of parallel silicon nanowires, placed perpendicularly to a silicon substrate (silicon nanowire forests), has been contacted and assembled in order to fabricate legs of a thermoelectric generator. This paper reports the measurement of the main parameter for thermoelectric applications, which is the thermal conductivity. The reported value, which confirms the strong reduction of the thermal conductivity in nanostructures, is measured on a large amount (> 10 7 ) of parallel nanowires with a diameter variable in the range 60 -120 nm, and takes into account eventual non uniformities which are unavoidable on surfaces of several mm 2 . As silicon nanowire forests are very thin, it has been necessary to develop a suitable measurement apparatus. The fabrication of devices based on silicon nanowire forests, the apparatus and the measurement procedure, as well as the the results, are illustrated and discussed.

Silicon is a material with very good thermoelectric properties, with regard to Seebeck coefficient and electrical conductivity. Low thermal conductivities, and hence high thermal to electrical conversion efficiencies, can be achieved in nanostructures, which are smaller than the phonon mean free path but large enough to preserve the electrical conductivity. We demonstrate that it is possible to fabricate a leg of a thermoelectric generator based on large collections of long nanowires, placed perpendicularly to the two faces of a silicon wafer. The process exploits the metal assisted etching technique which is simple, low cost, and can be easily applied to large surfaces. Copper can be deposited by electrodeposition on both faces, so that contacts can be provided, on top of the nanowires. Thermal conductivity of silicon nanowire forests with more than 10 nanowires mm have been measured; the result is comparable with that achieved by several groups on devices based on few nanowires. On the basis of the measured parameters, numerical calculations of the efficiency of silicon-based thermoelectric generators are reported, and the potentialities of these devices for thermal to electrical energy conversion are shown. Criteria to improve the conversion efficiency are suggested and described.

We present a technique for the fabrication of an electrical (and thermal) contact on the top ends of a large number of vertical silicon nanowires, which are fabricated perpendicularly to a silicon wafer (silicon nanowire forest). The technique is based on electrochemical deposition of copper and has been developed on silicon nanowire forests, fabricated by metal assisted chemical etching. We demonstrate that copper grows selectively only on the top end of the silicon nanowires, forming a layer onto the top of the forest. The presence of a predeposited metal seed is fundamental for the selective growth, meanwhile the process is very strong with respect to other parameters, such as concentration of the electrolytic solution and current density, used during the metal deposition. Typical I-V characteristics of top-to-bottom conduction through silicon nanowire forests with different n-doping are shown and discussed.

Complementary electronics has represented the corner stone of the digital era, and silicon technology has enabled this accomplishment. At the dawn of the flexible and wearable electronics age, the seek for new materials enabling the integration of complementary metal-oxide semiconductor (CMOS) technology on flexible substrates, finds in low-dimensional materials (either 1D or 2D) extraordinary candidates. Here, we show that the main building blocks for digital electronics can be obtained by exploiting 2D materials like molybdenum disulfide, hexagonal boron nitride and 1D materials such as carbon nanotubes through the inkjet-printing technique. In particular, we show that the proposed approach enables the fabrication of logic gates and a basic sequential network on a flexible substrate such as paper, with a performance already comparable with mainstream organic technology.