This paper introduces our original implementation of the combination of simplification before and during generation techniques to enable the approximated symbolic analysis of large analog circuits. Special emphasis is paid to the circuit reduction techniques embedded in the simplification before generation module. Experimental results of the application of the symbolic analysis methodology are shown which demonstrate its capability to provide interpretable symbolic expressions.

This paper addresses the automated parameter extraction of Random Telegraph Noise (RTN) models in nanoscale field-effect transistors. Unlike conventional approaches based on complex extraction of current levels and timing of trapping/detrapping events from individual defects in current traces, the proposed approach performs a simple processing of current traces. A smart optimization problem formulation allows to get distribution functions of the amplitude of the current shifts and of the number of active defects vs. time.

PUFs have emerged as an alternative to traditional Non-Volatile Memories in the field of hardware security. In this paper, a novel PUF is proposed that uses the Random Telegraph Noise phenomenon as the underlying source of entropy. This phenomenon manifests as discrete and random shifts in the drain current of transistors and it is characterized by several parameters like the number of the defects in the device, as well as the emission and capture time constants and current shifts of these defects. Using the recently reported Maximum Current Fluctuation metric, it is possible to condense all this information and use it for the PUF design. By forming pairs of transistors, measuring, and comparing their Maximum Current Fluctuation over a given time interval, we demonstrate using numerical experiments that it is possible to obtain a PUF. Furthermore, the results reported here show that this RTNbased PUF matches, and even outperforms, other silicon PUFs in terms of uniqueness, unpredictability, and reliability with an evident advantage in silicon area.