Abstract:A linearization technique for improving the class-E power amplifier (PA)'s adjacent channel power ratio (ACPR) is proposed. The design is simulated in a 2-µ m InGaP/GaAs heterojunction bipolar transistor process. The integration of a passive predistorter at the input of the PA linearizes the proposed architecture. At a 29-dBm output power, the PA's ACPR is indicated to be -51 dBc, meeting the stringent code division multiple access regulation. At this exact output power, the simulated power added efficiency is 55% with the collector voltage headroom consumption of 3.4 V. The input return loss, S11, of the PA is simulated as -12.5 dB. With an active finger print dimension of 1000 µ m × 750 µ m, the proposed PA is well suited for the application of mobile wireless communication.

For the first time, a new circuit to extend the linear operation bandwidth of a LTE (Long Term Evolution) power amplifier, while delivering a high efficiency is implemented in less than 1 mm2 chip area. The 950 µm × 900 µm monolithic microwave integrated circuit (MMIC) power amplifier (PA) is fabricated in a 2 µm InGaP/GaAs process. An on-chip analog pre-distorter (APD) is designed to improve the linearity of the PA, up to 20 MHz channel bandwidth. Intended for 1.95 GHz Band 1 LTE application, the PA satisfies adjacent channel leakage ratio (ACLR) and error vector magnitude (EVM) specifications for a wide LTE channel bandwidth of 20 MHz at a linear output power of 28 dBm with corresponding power added efficiency (PAE) of 52.3%. With a respective input and output return loss of 30 dB and 14 dB, the PA’s power gain is measured to be 32.5 dB while exhibiting an unconditional stability characteristic from DC up to 5 GHz. The proposed APD technique serves to be a good solution to improve linearity of a PA without sacrificing other critical performance metrics.