In this paper we propose a baseband noise-canceling receiver architecture to increase in-band linearity. Key feature of the architecture is that all active circuits are in baseband, including the LNTA. The receiver targets high IF bandwidths, enabled by a TIA composed of an OpAmp using only inverters. The receiver is fabricated in 22nm FDSOI CMOS. Measured results show an in-band IIP3 of > 9dBm for an IF bandwidth of 175MHz with sub-5dB NF across 1-6GHz LO.

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A highly integrated dual conversion heterodyne GPS receiver is reported. The receiver chip includes a 2.9dB NF LNA, an image-reject mixer with 32dB image rejection. The on-chip IF chain, which consists of a VGA, a Znd mixer and filtering, has a maximum gain of 83dB, a gain range of 45dB and a 7dB NF. A 4-bit ADC is integrated on chip for enhanced SNR. The PLL with its VCO are also integrated. The total NF is 3dB with a total 121dB voltage gain. The chip consumes 132mW at 2. 7%'.

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