We present a novel passivating contact structure based on a nanostructured siliconbased layer. Traditional poly-Si junctions feature excellent junction characteristics but their optical absorption induces current losses when applied to the solar cell front side. Targeting enhanced transparency, the poly-Si layer is replaced with a double-layer stack consisting of a nanostructured silicon oxide capped with a nanocrystalline silicon (nc-Si) layer. The nanostructured silicon oxide layer consists of an amorphous SiOx matrix with incorporated Si filaments connecting one side of the layer to the other, and is referred to as nanocrystalline silicon oxide (nc-SiOx) layer. We investigate passivation quality, measured as saturation current density, and nanostructural changes, characterized by Raman spectroscopy and transmission electron microscopy, carefully studying the influence of annealing dwell temperature. Excellent surface passivation on n-type and also p-type wafers is shown. An optimum annealing temperature of 950 °C is found, resulting in a saturation current density of 8.8 fA cm-2 and 11.0 fA cm-2 for n-type and p-type wafers, respectively. Efficient current extraction is presented with specific contact resistivities of 86 mΩ cm 2 on n-type wafer and 19 mΩ cm 2 on p-type wafers, respectively. Highresolution transmission electron microscopy reveals that the layer stack consists of intermixed SiOx and Si phases with the Si phases being partly crystalline already in the asdeposited state. Thermal annealing at temperatures ≥ 850 °C further promotes crystallization of the Si-rich regions. We show that the addition of the SiOx phase enhances the thermal stability of the contact and we expect it to allow to tune the refractive index and improve transparency while still providing efficient electrical transport thanks to the crystalline Si phase, which extends throughout almost the entire layer.

The use of passivating contacts compatible with typical homojunction thermal processes is one of the most promising approaches to realizing high-efficiency silicon solar cells. In this work, we investigate an alternative rear-passivating contact targeting facile implementation to industrial p-type solar cells. The contact structure consists of a chemically grown thin silicon oxide layer, which is capped with a boron-doped silicon-rich silicon carbide [SiC(p)] layer and then annealed at 800-900 °C. Transmission electron microscopy reveals that the thin chemical oxide layer disappears upon thermal annealing up to 900 °C, leading to degraded surface passivation. We interpret this in terms of a chemical reaction between carbon atoms in the SiC(p) layer and the adjacent chemical oxide layer. To prevent this reaction, an intrinsic silicon interlayer was introduced between the chemical oxide and the SiC(p) layer. We show that this intrinsic silicon interlayer is beneficial for surface passivation. Optimized passivation is obtained with a 10-nm-thick intrinsic silicon interlayer, yielding an emitter saturation current density of 17 fA cm on p-type wafers, which translates into an implied open-circuit voltage of 708 mV. The potential of the developed contact at the rear side is further investigated by realizing a proof-of-concept hybrid solar cell, featuring a heterojunction front-side contact made of intrinsic amorphous silicon and phosphorus-doped amorphous silicon. Even though the presented cells are limited by front-side reflection and front-side parasitic absorption, the obtained cell with a V of 694.7 mV, a FF of 79.1%, and an efficiency of 20.44% demonstrates the potential of the p/p-wafer full-side-passivated rear-side scheme shown here.

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The silicon heterojunction (SHJ) technology has already proven its ability to produce high-efficiency devices, and very competitive production costs at the mass production level can be potentially reached by integrating latest developments. In this work, several of such technology developments are presented related to the PECVD and metallization steps. PECVD processes were developed in a large-area reactor, showing excellent thickness uniformity over the full reactor area (< 4%) and state-of-theart passivation level (> 16 ms). Improvements in screen-printing permitted to reduce the finger width down to 40 m. A 21.9% 6-inch busbar-less cell with only 25 mg of Ag was produced, resulting in Ag cost of only 0.22 €cts/Wp. A complete SHJ process for full-area 6-inch cells has been established using industry-compatible processes, with a record efficiency of 22.8% and V oc s above 740 mV (CZ n-type). The use of 4 cm 2 SHJ cells for low-concentration applications was investigated at different illumination levels and temperatures. With optimized front grid designs (Cu electro-plated fingers), efficiencies can be maintained around 20% at 10 suns. Thanks to a temperature-assisted improvement in carrier transport, the cell temperature coefficient improves with illumination, showing even positive values above 35 suns. This suggests a strong potential of SHJ cells for low-concentration PV.

We report independently confirmed 22.15% and record 22.58% power conversion efficiencies, for thin (130 μm-140 μm) p-and n-type mono-like Si solar cells, respectively. We comparatively assessed advanced n-type and p-type mono-like silicon wafers for potential use in low-cost high-efficiency solar cell applications by using phosphorus diffusion gettering for material-quality improvement and silicon heterojunction solar cell fabrication for assessment of performance in high-efficiency photovoltaic device architecture. We show that gettering improves material quality and device properties significantly, depending on the type of doping (n-type or ptype), wafer position in the ingot, drive-in temperature and cooling profile. Owing to the high open circuit voltage (725 mV), the record n-type solar cell also represents the highest reported solar cell efficiency for cast silicon to date.