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An ultra-low-power DSP decimationlinterpolation structure is described demonstrating how algorithmic and architectural schemes were employed for ultimate power efficiency in a DSP based chip set for audio applications. This circuit was designed and synthesised for a low VT 0.35 pm CMOS process allowing Nyquist rate signals to be decimated from a high OSR S A frontend and interpolation post voice processing at the back end. The DSP has been fabricated and operates down to 0.9 V. At 1.25 V, its current consumption is only 90 pA.

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