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Low-Density Fan-Out (LDFO) (or fan-out wafer-level packaging) technologies are getting significant attention for heterogeneous system integration in many applications. Despite many studies, excessive wafer warpage is still a challenge for many process steps in these technologies. Therefore, the systematic study is carried out to understand the physics of wafer warpage focusing on the interactions between the silicon (Si) and the epoxy molding compound (EMC). The study started with analytical calculations and finite element (FE) analyses of simple mold/Si bilayer wafer bow for the initial benchmarking. The actual 8″ mold/Si wafer warpage measurements are performed using a newly developed measurement system featuring a 3-point support and an in-situ temperature measurement platform. The finite element model is calibrated with respect to measured wafer warpage showing bifurcation behavior by incorporating the cure shrinkage, mold layer thickness variation, perturbation force, gravity and the actual mold material properties measured by dynamic mechanical analysis (DMA) and thermomechanical analysis (TMA). Also, the FE models with and without rigid contact support are validated showing a good match with measured wafer bow for different silicon thicknesses. Next, the study was further widened to realistic 12″ reconstituted wafers using the validated FE analysis approach. Interestingly, these wafers also exhibit the bifurcation effect and the bifurcation region is analyzed for the relevant range of die and overmold thicknesses for two mold materials. A virtual design of experiments (DOE) quantified these influences for different die and mold thicknesses, die occupation rate and mold materials. These studies provide good practical guidance for the optimal LDFO design to avoid excessive warpage.

Overview: Fan-In WLP plays crucial role on today's high density, high performance IC Packaging. 300 mm wafer processing addresses cost-per-unit reduction and volume demand. Results of Spheron Fan-In WLCSP Technology Qualification and 200 mm to 300 mm Scale Up at Nanium, using FlipChipInternational Technology Licensing

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