The paper presents the steps for the parametric finite element model creation of the wafer, material characterization of the adhesive tape, analytical and finite element study of the wafer warpage considering the bifurcation, gravity effect on the wafer bow assessing the warpage of mold/Si bilayered structure under thermal loading. The analytical results are compared to finite element analyses (FEA) considering the linear and nonlinear deflection. Consequently, the FEA approach has been used to study the deformation of 12" reconstituted wafers in their FOWLP fabrication process. By changing the temperature, the deformation of the wafer shows a bifurcation point, at which the warpage changes between the spherical and cylindrical shapes. The bifurcation region has been analyzed for the relevant range of overmold thicknesses in order to provide the guidance to optimum wafer and process designs that avoid the excessive warpage. For different wafer structures, the study determines also the effects of the gravitational force on the wafer bow as well as its influence in combination with the thermal mismatch. Finally, the FOWLP process induced warpage has been demonstrated by FEA incorporating the geometrical nonlinearity, gravity and ground support by means of contact elements.

A modular system of parametric FE models is created using ANSYS parametric design language (APDL) for automated virtual prototyping of current and future System-in-Package (SiP) solutions based on fan-out-wafer-level-packaging (FOWLP) technologies. The principles of the hierarchical architecture are described and instructive examples are given for all levels, i.e., from the part models to the four demonstrator packages. Further, the results of first simulations addressing the typical load case of temperature cycling between -40°C and 125°C clearly demonstrate the validity of the approach as they agree to the experimental finding. The system of models is now applicable to a large variety of future SiP products based on FOWLP. It will allow virtual prototyping, i.e., replace time consuming experimental tests during the product definition phase. Keywords-System-in-Package (SiP), fan-out wafer level packaging (FOWLP), Parametric FE modelling, thermal cycling (TC), Package on Package (PoP)Family 1 Family 3 Family 2

Low-Density Fan-Out (LDFO) (or fan-out wafer-level packaging) technologies are getting significant attention for heterogeneous system integration in many applications. Despite many studies, excessive wafer warpage is still a challenge for many process steps in these technologies. Therefore, the systematic study is carried out to understand the physics of wafer warpage focusing on the interactions between the silicon (Si) and the epoxy molding compound (EMC). The study started with analytical calculations and finite element (FE) analyses of simple mold/Si bilayer wafer bow for the initial benchmarking. The actual 8″ mold/Si wafer warpage measurements are performed using a newly developed measurement system featuring a 3-point support and an in-situ temperature measurement platform. The finite element model is calibrated with respect to measured wafer warpage showing bifurcation behavior by incorporating the cure shrinkage, mold layer thickness variation, perturbation force, gravity and the actual mold material properties measured by dynamic mechanical analysis (DMA) and thermomechanical analysis (TMA). Also, the FE models with and without rigid contact support are validated showing a good match with measured wafer bow for different silicon thicknesses. Next, the study was further widened to realistic 12″ reconstituted wafers using the validated FE analysis approach. Interestingly, these wafers also exhibit the bifurcation effect and the bifurcation region is analyzed for the relevant range of die and overmold thicknesses for two mold materials. A virtual design of experiments (DOE) quantified these influences for different die and mold thicknesses, die occupation rate and mold materials. These studies provide good practical guidance for the optimal LDFO design to avoid excessive warpage.

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