In this paper, we study a lightweight algorithm for distributed parameter estimation in a heterogeneous network in the presence of adversary nodes. All nodes interact under a local broadcast model of communication in a time-varying network comprised of many inexpensive normal nodes, along with several more expensive, reliable nodes. Either the normal or reliable nodes may be tampered with and overtaken by an adversary, thus becoming an adversary node. The reliable nodes have an accurate estimate of their true parameters, whereas the inexpensive normal nodes communicate and take difference measurements with neighbors in the network in order to better estimate their parameters. The normal nodes are unsure, a priori, about which of their neighbors are normal, reliable, or adversary nodes. However, by sharing information on their local estimates with neighbors, we prove that the resilient iterative distributed estimation (RIDE) algorithm, which utilizes redundancy by removing extreme information, is able to drive the local estimates to their true parameters as long as each normal node is able to interact with a sufficient number of reliable nodes often enough and is not directly influenced by too many adversary nodes.

This paper presents an FPGA-based architecture for local tone mapping of gray scale high dynamic range images. The architecture is described in VHDL and has been synthesized using Altera Quartus tools. It achieves an operating frequency consistent with a video rate of 60 frames per second for a frame of 1,024 9 768 pixels. The proposed architecture is a modification of the nine-scale Reinhard operator. Approximations to the original Reinhard operator ensure that the operator is amenable to implementation in hardware. A peak signal-to-noise ratio study shows that our fixed-point hardware approximation produces results similar to a floating-point original.

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This thesis presents a real-time hardware implementation of a gradient domain high dynamic range compression algorithm; this technique is useful for processing high dynamic range (HDR) images to be able to view them on standard display devices. The hardware implementation is described in VHDL and synthesized for a field programmable gate array (FPGA) device. The maximum operating frequency achieved is fast enough to process high dynamic range videos with one megapixel per frame at a rate of about 100 frames per second. The hardware is tested on standard HDR images from the Debevec library. The output images have good visual quality and are similar to the output images obtained using floating-point arithmetic. An alternate hardware implementation that does not involve any multipliers is also discussed. The inverse gradient transformation required for reconstructing back the image from the manipulated gradients is implemented by means of a local Poisson solver that utilizes only local information around each pixel along with special boundary conditions. The local Poisson solver requires a small and fixed amount of hardware and memory for any image size. The quality of the images obtained using our local Poisson solver for both fixed-point and floating-point implementations is compared to the quality of images produced by a system that solves the Poisson equation using a full-image fast Fourier transform (FFT).

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