Estimating the impact of Single Event Effects (SEEs) on SRAM-based FPGA devices is a major issue in order to adopt them in radiation environments such as space or high altitude. Among the available approaches, we proposed an analytical method to predict SEE effects based on the analysis of the circuit the FPGA implements, which does not require either simulation or fault injection. In this paper we provide an experimental validation of this approach, by comparing the results it provides with those coming from accelerated testing. We adopted our analytical method for computing the error cross section of a design implemented on SRAM-based FPGA devices. We then compared the obtained figure with that obtained by accelerated testing. Experimental analysis demonstrated that accelerated testing closely match the figures the analytical method provides.

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Expérience GANILInternational audienceThis paper presents experimental data showing heavy ions inducing gate degradation in power MOSFETs. In the experiments, backside and front-side irradiations are performed. During backside irradiation, the heavy ion ranges are tuned in such way to control whether they hit the gate or not. Gate-to-source current Igss ( ) is measured versus heavy ions (H.I.) fluence . Post-irradiation- gate-stress-test (PGST) allows measurement of gate breakdown voltage VBD( ) which is observed to decrease with (H.I.) fluence. Based on these experimental results, a hypothesis of substrate- generated carriers impact overlap of multiple strikes may explain gate degradation until SEGR triggering. This last hypothesis is supported by a statistical model approach of heavy ions multiple impacts

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