Great efforts have been made for the integration of high dielectric constant (Ba,Sr)Ti03 (BST) capacitors into DRAMs. This paper presents the current state of the art in BST capacitor technology for Gbit-scale DRAMs, with emphasis on key technical issues for process integration, including electrode materials, barrier layers, and also BST films themselves. The problems which may remain to be solved are also discussed to realize the goal: a barrier layer on top electrode for back-end processes, reliability of integrated BST capacitors, and further improvement of coverage properties of BST films and cell-plate metals.been achieved so far. On the other hand, in a 3-D stack, the sidewall capacitance increases with increasing the height of patterned stlorage nodes, which gives the scaling of this structure down to Gbit dimensions. These 3-D stack capacitors may be further classed under two types, having tapered and vertical storage nodes. It should be noted that for the 3-D stack with tapered storage nodes, their height is limited by geometrical conditions where the bottom of tapered electrodes would be buried in the small spacing between storage nodes; e.g., for a typical sidewall angle 8=70", the hleight of storage nodes is limited to D10.25 pm in 0.18 pm rule and to DI0.18 pm in 0.13 prn rule (4-Gbit), which in turn requires &,I0.34 nm and t&0.18 MI, respectively Introduction Electrode Materials From the technology perspective, the DRAM cell is rapidly shrinking as shown in Fig. 1, which in turn leads to aggressive scaling of memory cell capacitors while maintaining the storage capacitance therein.The minimum storage capacitance required remains to be C,225 @/cell even for Gbit-scale DRAMs, relying on the sense amplifier sensitivity, data retention time, and soft error immunity. Capacitor technology with high dielectric constant BST films has been developed to meet these requirements [ 1-51, as an alternative to capacitors using conventional dielectric materials such as Si3N4/SiOz and Taz05 which are now being actively studied in combination with HSG for 256-Mbit DRAMs. This paper presents the current state of the art in BST capacitor technology for Gbit-scale DRAMs and DRAM-embedded system LSIs, with emphasis on key technical issues for process integration such as electrode materials, barrier layers, and BST films themselves. The problems which may remain to be solved are also discussed to realize the goal.There are"a few different types of BST capacitor structures: a planar and a three-dimensional (3-0) stack capacitor, as shown in Table 1. The planar stack is scalable to 256-Mbit dimensions at most, as can be seen in Fig. 2, because the capacitance comes only from a planar dielectric layer between the bottom and top electrodes (i.e., storage node and cell plate). The equivalent oxide thickness required for a planar type (D=O) is around b=O.12 nm in 0.18 pm (1-Gbit) rule, which is far from the minimum %=0.24 nm that has The electrodle material for storage nodes is still the number one technical issue, because it g...

High Jc Y1Ba2Cu3O7−x superconducting thin and thick films were prepared onto SrTiO3 (100) substrates at 700 °C by metalorganic chemical vapor deposition (MOCVD) technique using a single solution source. A mixture of Y, Ba, and Cu β-diketonate chelates was dissolved in tetrahydrofuran as a solution source. Zero resistance transition temperature and critical current density at 77 K, 0 T for thin and thick films were 90 K and 2.73×106 A/cm2, 91 K and 3.1×105 A/cm2, respectively. X-ray diffraction measurement indicated that the thin film grew epitaxially with the c-axis orientation perpendicular to the surface of the substrate and the thick films mainly consisted of a-axis orientation.

We study the application of (Ba,Sr)TiO3 (BST) films prepared by chemical vapor deposition (CVD) method to ∼0.13-µm-scale devices, for example, 4Gbit dynamic random access memories (DRAMs), whose minimum feature size and height of storage nodes are around 0.13 and 0.36 µm, respectively. It is necessary for these devices to obtain a conformal step coverage of the BST films of more than 80% at an aspect ratio of 3–5, along with an equivalent SiO2 thickness (t eq) of 0.5 nm. Recently, a new Ti source, Ti(t-BuO)2(DPM)2 [bis (t-butoxy) bis (dipivaloylmethanato) titanium], whose Ti ion is surrounded by four large organic ligands, was developed. It is more stable in THF (tetrahydrofuran; C4H8O) solution and in the vapor phase than conventional Ti sources such as TiO(DPM)2 [oxo bis (dipivaloylmethanato) titanium]. In fact, the step coverages of the BST films using Ti(t-BuO)2(DPM)2 were found to be 80% and 70% at aspect ratios of 3.3 and 5, respectively, which were much better than those of films using TiO(DPM)2. Moreover, the electrical properties of the BST films using Ti(t-BuO)2(DPM)2 were t eq =0.44 nm and a leakage current J L of 2.8× 10-8 A/cm2 (+1.1 V) for a film of 24 nm thickness after post-annealing. These characteristics meet the requirements of the 4Gbit DRAM capacitors.

Phase transitions in MnTiF6.6H20 and ZnTiF6.6H20 have been observed by studying their IR spectra at different temperatures. The librational modes of the water molecule change significantly around the transition temperature.

We investigated the critical current density and the flux creep in melt-processed Bi-Pb-Sr-Ca-Cu-O for the purpose of studying the existence of strong flux pinning forces due to normal conducting precipitates. We fabricated samples with a similar microstructure to melt-processed Y-Ba-Cu-O and Tl-Sr-Ca-Cu-O having a strong pinning force. When the matrix was (Bi, Pb)2Sr2Ca1Cu2O y (2212) phase, the irreversibility field B irr was expressed as B irr\propt(1-T/T c)3/2, which suggested that the expected flux pinning was due to normal conducting precipitates. A part of the matrix was transformed to (2223) phase by the postannealing of the sample; however, the superconducting properties were inferior to those observed in (2223) polycrystals.