We report that the ion implantation of a small dose of Mo into a silicon substrate before the deposition of a thin film of Ti lowers the temperature required to form the commercially important low resistivity C54 -TiSi 2 phase by 100-150°C. A lesser improvement is obtained with W implantation. In addition, a sharp reduction in the dependence of C54 formation on the geometrical size of the silicided structure is observed. The enhancement in C54 formation observed with the ion implantation of Mo is not explained by ion mixing of the Ti/Si interface or implant-induced damage. Rather, it is attributed to an enhanced nucleation of C54 -TiSi 2 out of the precursor high resistance C49-TiSi 2 phase.
We demonstrate that the temperature at which the C49 TiSi2 phase transforms to the C54 TiSi2 phase can be lowered more than 100 °C by alloying Ti with small amounts of Mo, Ta, or Nb. Titanium alloy blanket films, containing from 1 to 20 at. % Mo, Ta, or Nb were deposited onto undoped polycrystalline Si substrates. The temperature at which the C49–C54 transformation occurs during annealing at constant ramp rate was determined by in situ sheet resistance and x-ray diffraction measurements. Tantalum and niobium additions reduce the transformation temperature without causing a large increase in resistivity of the resulting C54 TiSi2 phase, while Mo additions lead to a large increase in resistivity. Titanium tantalum alloys were also used to form C54 TiSi2 on isolated regions of arsenic doped Si(100) and polycrystalline Si having linewidths ranging from 0.13 to 0.56 μm. The C54 phase transformation temperature was lowered by over 100 °C for both the blanket and fine line samples. As the concentration of Mo, Ta, or Nb in the Ti alloys increase, or as the linewidth decreases, an additional diffraction peak appears in in situ x-ray diffraction which is consistent with increasing amounts of the higher resistivity C40 silicide phase.
The development of DRAM at IBM produced many novel processes and sophisticated analysis methods. Improvements in lithography and innovative process features reduced the cell size by a factor of 18.8 in the time between the 4Mb and 256Mb generations. The original substrate piate trench cell used in the 4Mb chip is still the basis of the 256Mb technology being developed today. This paper describes some of the more important and interesting innovations introduced in IBM CMOS DRAMs. Among them, shallow-trench isolation, 1-line and deep-UV (DUV) lithography, titanium salicidation, tungsten stud contacts, retrograde n-well, and planarized bacl(-end-ofline (BEOL) technology are core elements of current state-of-the-art logic technology described In other papers in this issue. The DRAM specific features described are borderless contacts, the trench capacitor, trench-isolated cell devices, and the "strap." Finally, the methods for study and control of leakage mechanisms which degrade DRAM retention time are described.^Copyright 1995 by International Business Machines Corporation. Copying in printed form for private use is permitted witiiout payment of royalty provided tliat (1) each reproduction is done without alteration and (2) the Journal reference and IBM copyright notice are included on the first page. The title and abstract, but no other portions, of this paper may be copied or distributed royalty free without further permission by computer-based and other information-service systems. Permission to republish any other portion of this paper must be obtained from the Editor.
We demonstrate that the formation temperature of the C54 TiSi2 phase from the bilayer reaction of Ti on Si is lowered by approximately 100 °C by placing an interfacial layer of Mo or W between Ti and Si. Upon annealing above 500 °C, the C49 TiSi2 phase forms first, as in the reaction of Ti directly on Si. However, the temperature range over which the C49 phase is stable is decreased by approximately 100 °C, allowing C54 TiSi2 formation below 700 °C. Patterned submicron lines (0.25−1.0 μm wide) fabricated without the Mo layer contain only the C49 TiSi2 phase after annealing to 700 °C for 30 s. With a Mo layer less than 3 nm thick between Ti and Si, however, a mixture of C49 and C54 TiSi2 was formed, resulting in a lower resistivity. The enhanced formation of the C54 TiSi2 is attributed to an increased density of nucleation sites for the C49-C54 phase transformation, arising from a finer grained precursor C49 phase.
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