Abstract-An integrated voltage regulator (IVR) is. At maximum load current, 69% conversion efficiency and 1.8 V:1.2 V conversion ratio the FEOL current density reaches 22.6 and inductor current density reaches 3.21 .

Energy consumption is a dominant constraint on the performance of modern microprocessors and systems-on-chip. Dynamic voltage and frequency scaling (DVFS) is a promising technique for performing "on-the-fly" energy-performance optimization in the presence of workload variability. Effective implementation of DVFS requires voltage regulators that can provide many independent power supplies and can transition power supply levels on nanosecond timescales, which is not possible with modern board-level voltage regulator modules (VRMs) [1]. Switched-inductor integrated voltage regulators (IVRs) can enable effective implementation of DVFS, eliminating the need for separate VRMs and reducing power distribution network (PDN) impedance requirements by performing dc-dc conversion close to the load while supporting high peak current densities [2][3]. The primary obstacle facing development of IVRs is integration of suitable power inductors. This work presents an early prototype switched-inductor IVR using 2.5D chip stacking for inductor integration.Figure 23.1.1 shows the complete 2.5D chip stack. A prototype IC, fabricated in IBM's 45nm SOI process, contains buck converter circuitry, decoupling capacitance and a realistic digital load. This IC is flip-chip mounted onto an interposer that holds custom fabricated coupled power inductors for the buck converter while breaking out signals and the 1.8V input power supply to wirebond pads on the perimeter of the interposer. . The pole in both RC low-pass filters is chosen to be below f s so that the steady state amplitude of V REF,I and V FB,I is around 150mV, which gives a small signal feedback gain of ~30V/V and ensures stable loop dynamics. In steady state, V FB,I will slew behind V REF,I and the resultant evaluation of the comparator causes V BRIDGE to closely track V PWM . In the event of a large load current transient, the error in the output voltage, V OUT , will couple across C FB onto V FB,I and the comparator will react immediately to reduce overshoot in V OUT . This fast non-linear response can reduce the required decoupling capacitance on the output voltage [3]. Also residing on the IC is a 64-tile network-on-chip (NoC) consisting of four parallel, heterogeneous, physical network planes with independent frequency domains. The NoC provides realistic load behavior and supports experimentation on supply noise and DVFS. In addition, an artificial load on the IC is capable of generating large current transients with ~2A/100ps slew. A total of 48nF of deep-trench (DT) and thick oxide MOS capacitance decouples V OUT and occupies 0.40mm 2 , while 21nF of DT occupying 0.52mm 2 decouples the 1.8V input supply to compensate for the large PDN impedance.Two sets of four coupled power inductors, shown in Fig. 23.1.3, are fabricated on the silicon interposer such that one terminal of each inductor connects to a pair of V BRIDGE C4 receiving pads, while the opposite terminals are shorted and connected to several pads across the interposer for distribution of V OUT . The inductor top...

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This paper describes trends in the storage technologies associated with Linear Tape Open (LTO) Tape cartridges, hard disk drives (HDD), and NAND Flash based storage devices including solid-state drives (SSD). This technology discussion centers on the relationship between cost/bit and bit density and, specifically on how the Moore’s Law perception that areal density doubling and cost/bit halving every two years is no longer being achieved for storage based components. This observation and a Moore’s Law Discussion are demonstrated with data from 9-year storage technology trends, assembled from publically available industry reporting sources.

Thin-film ferromagnetic inductors show great potential as the energy storage element for integrated circuits containing on-chip power management. In order to achieve the high energy storage required for power management, on-chip inductors require relatively thick magnetic yoke materials (several microns or more), which can be readily deposited by electroplating through a photoresist mask as demonstrated in this paper, the yoke material of choice being Ni 45 Fe 55 , whose properties of relatively high moment and electrical resistivity make it an attractive model yoke material for inductors. Inductors were designed with a variety of yoke geometries, and included both single-turn and multi-turn coil designs, which were fabricated on 200 mm silicon wafers in a CMOS back-end-of-line (BEOL) facility. Each inductor consisted of electroplated copper coils enclosed by the electroplated Ni 45 Fe 55 yokes; aspects of the fabrication of the inductors are discussed. Magnetic properties of the electroplated yoke materials are described, including high frequency permeability measurements. The inductance of 2-turn coil inductors, for example, was enhanced up to about 6 times over the air core equivalent, with an inductance density of 130 nH/mm 2 being achieved. The resistance of these non-laminated inductors was relatively large at high frequency due to magnetic and eddy current losses but is expected to improve as the yoke material/structure is further optimized, making electroplated yoke-containing inductors attractive for dc-dc power converters.