POWER5 offers significantly increased performance over previous POWER designs by incorporating simultaneous multithreading, an enhanced memory subsystem, and extensive RAS and power management support. The 276M transistor processor is implemented in 130nm silicon-on-insulator technology with 8-level of Cu metallization and operates at >1.5 GHz. General TermsDesign Keywords POWER5, Microprocessor Design, Simultaneous Multi-threading (SMT), Temperature Sensor, Power Reduction, Clock Gating POWER5 TM is the next generation of IBM's POWER microprocessors. This design, shown below in Figure 1, sets a new standard of industry-leading server performance by incorporating simultaneous multithreading (SMT), an enhanced distributed switch and memory subsystem supporting 1-64w SMP, and extensive RAS support. First pass hardware using IBM's 130nm silicon-on-insulator technology operates above 1.5GHz at 1.3V.POWER5's dual-threaded SMT [1] creates up to two virtual processors per core, improving execution unit utilization and masking memory latency. Although a simplistic SMT implementation promised ~20% performance improvement, resizing critical micro-architectural resources almost doubles in many cases the SMT performance benefit at a 24% area cost per core.The two SMT cores interface with an enhanced memory subsystem. The cache hierarchy includes a larger (1.9MB) L2 cache, reduced L3 latency, and a larger (36MB) L3 cache located on a custom DRAM companion chip. The new on-chip main memory controller improves latency and the enhanced interconnect fabric extends SMP scalability. Figure 2 depicts the microarchitectural changes introduced with POWER5 chip.

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A BiCMOS low-power, 5-volt single chip read channel IC is presented in this paper. This device contains all the functional blocks needed to implement a high performance read channel, including the AGC, programmable active filter, pulse detector, servo demodulator, data separator, and time base generator. External components are minimized for small-form factor evolution and cost reduction. This versatile device supports 8-24 Mbit/s data rate operation in 1,7 RLL format. It also supports constant density recording. Typical power dissipation is 400 mW. Programmability, testability, and configuration of this device are achieved by a bidirectional serial microprocessor i n t d a and internal registers. L INTRODUCTIONTraditionally, read channel electronics are composed with VLSI chip sets [1,2]. Today hard disk drives are rapidly evolving towards smaller form factors, lower power, higher data rates, as well as reduced cost. This results in a need for single-chip solutions for read channel electronics. The BiCMOS process, which provides the well-known inherent properties of Bipolar and CMOS technologies, is the best technology of choice to meet the performance and power requirements. In this paper we present a complete read channel combo device designed using an advanced 1-um BiCMOS technology. It supports 8-24 Mbiffs data rates in hard disk drives employing constant density recording techniques for capacity efficiency. Figure 1 shows a typical disk chive read channel system. Practically the r d w r i t e pre-amplifier is located as close to the magnetic head and magnetic medium as possible and the controller itself is a VLSI device. Thus our read channel combo integrates the automatic gain control (AGC) circuit, lowpass filter/equalizer, pulse detector and data separator. It also includes a servo demodulator for capturing servo information and a time base generator for write clock generation for constant density recording. IL FUNCTIONAL DESCRIPTIONThe detailed block diagram of the read channel combo is shown in Figures 2(a) and (b) which are defmed as the front end and back end of the combo. To avoid offset problems as well as for testability reasons, the analog inputs and outputs are AC coupled through external capacitors in the front end. Two external resistors, RX and RR set the reference currents for two 7-bit internal DACs whose programmable output currents determine the cut-off kequency of the filter and the data rate of the combo, respectively. Multiplexed test point output pins, M"1, MTPZ, and M " 3 , are incoxporated to monitor either input signals to the phase detector or internal clock and data signals of the pulse detector or the output of the time base generator. These pseudo ECL test points are enabled only in test modes. Loop filters for the PLLs of the data separator and the time base generator are fully-differential in order to suppress the common-mode noise generated by its counterpart PLL. Throughout this combo, most signals are transmitted differentially to ieduce common-mode noise coupling.Programm...