This methodology is used by both IBM ASIC and SoC designers, as well as OEM customers.A key focus of the IBM ASIC/SoC methodology, outlined in the first section of this paper, is the first-time-right methods of design and verification that maximize correct operation of the chip upon product integration. The second section of this paper describes advances in methodology that deal with the physical effects of shrinking device geometries and enable design using the performance and density capabilities available in the new technologies, and methodology advances that have improved design turnaround time (TAT) for large, complex designs. Upcoming nanometerlevel technologies present new opportunities to integrate systems on a single chip, including functional components of mixed libraries and mixed analog and digital design. The final section of this paper outlines strategies that are enabling SoC design at these levels.

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