The work presented here is an experimental study of four iterative algorithms for solving the Inverse Additive Singular Value Problem (IASVP). The algorithms are analyzed and evaluated with respect to different points of view: memory requirements, convergence, accuracy and execution time, in order to observe their behaviour with different problem sizes and to identify those capable to solve the problem efficiently.

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A fuzzy sets intersection procedure to select the optimum sizes of analog circuits composed of metal-oxidesemiconductor field-effect-transistors (MOSFETs), is presented. The cases of study are voltage followers (VFs) and a current-feedback operational amplifier (CFOA), where the width (W) and length (L) of the MOSFETs are selected from the space of feasible solutions computed by swarm or evolutionary algorithms. The evaluation of three objectives, namely: gain, bandwidth and power consumption; is performed using HSPICETM with standard integrated circuit (IC) technology of 0.35μm for the VFs and 180nm for the CFOA. Therefore, the intersection procedure among three fuzzy sets representing “gain close to unity”, ”high bandwidth” and “minimum power consumption”, is presented. The main advantage relies on its usefulness to select feasible W/L sizes automatically but by considering deviation percentages from the desired target specifications. Basically, assigning a threshold to each fuzzy set does it. As a result, the proposed approach selects the best feasible sizes solutions to guarantee and to enhance the performances of the ICs in analog signal processing applications.

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The problem tackled in this paper is the parallel construction of a unit triangular matrix with prescribed singular values, when these fulfill Weyl's conditions [9]; this is a particular case of the Inverse Singular Value Problem. A sequential algorithm for this problem was proposed in [10] by Kosowsky and Smoktunowicz. In this paper parallel versions of this algorithm will be described, both for shared memory and distributed memory architectures. The proposed parallel implementation is better suited for the shared memory paradigm; this is confirmed by the numerical experiments; the shared memory version, reaches an efficiency over 90%, and reduces substantially the execution times compared with the sequential algorithm.