Evolutionary Algorithms in the Optimal Sizing of Analog Circuits

Tlelo‐Cuautle, Esteban; Guerra-Gomez, I.; Fraga, Luis Gerardo de la; Flores-Becerra, Georgina; Polanco-Martagón, Said; Fakhfakh, Mourad; Reyes-García, Carlos A.; Rodríguez-Gómez, Gustavo; Reyes-Salgado, Gerardo

doi:10.1007/978-3-642-21705-0_5

Cited by 11 publications

(9 citation statements)

References 39 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Is for that reason that we apply heuristics herein for optimizing its performances, but the main goal is focused on showing that by applying our proposed CBBA approach, the execution of the three evolutionary algorithms (EAs): NSGA-II [13], MOEA/D [14] and MOPSO [15], is being improved and accelerated. The implementation details of those three EAs when applied to the optimal sizing of analog ICs can be found in [1], [2], [4], [6]. The inclusion of our proposed CBBA approach is straightforward but quite useful.…”

Section: Application Examplementioning

confidence: 99%

“…The sizing optimization of analog integrated circuits (ICs) by applying heuristic approaches has grown in the last decade [1]- [8]. For instance, evolutionary algorithms (EAs) are preferred because they provide a set of feasible solutions [4]. For EAs to work, one needs to specify: design variables, objectives, constraints, and search spaces.…”

Section: Introductionmentioning

confidence: 99%

“…The usefulness of our proposed CBBA approach is demonstrated by sizing the recycled folded cascode (RFC) operational transconductance amplifier (OTA) given in [9], by applying three EAs, namely: non-dominated sorting genetic algorithm (NSGA-II) [13], multi-objective EA with decomposition (MOEA/D) [14], and multi-objective particle swarm optimization (MOPSO) [15]. These EAs have been applied to sizing analog ICs in [1], [2], [4], [6]. In those references one can find their implementation details, and one can infer that at this moment any EA considers CBBA before starting the sizing optimization process.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Sizing Analog Integrated Circuits by Current-Branches-Bias Assignments with Heuristics

Guerra-Gomez

Tlelo‐Cuautle

2013

ElAEE

View full text Add to dashboard Cite

This work shows the usefulness of assigning current-branches-bias levels, in order to improve and accelerate the sizing optimization of MOSFET-based analog integrated circuits (ICs). That way, the proposed procedure relies on the search of current branches from the associated incidence matrix by applying a recursive technique for exploring circuit graphs. The goal is focused on determining the bounds of the width/length (W/L) search space for each MOSFET before starting the sizing optimization process. As a case of study, the proposed current-branches-bias assignment (CBBA) approach is applied in the sizing optimization of the recycled folded cascode operational transconductance amplifier by applying evolutionary algorithms (EAs). From the feasible optimization results, we conclude that our proposed CBBA approach enhances and accelerates the biasing and sizing of analog ICs by EAs.

show abstract

Section: Application Examplementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Sizing Analog Integrated Circuits by Current-Branches-Bias Assignments with Heuristics

Guerra-Gomez

Tlelo‐Cuautle

2013

ElAEE

View full text Add to dashboard Cite

show abstract

“…In state-of-the-art optimization procedures, these properties are mostly searched as a combination of more reliable, but slower metaheuristic algorithms [1][2][3][4][5][6] with faster, but less stable direct optimization methods [7][8][9][10]. We have suggested an original combination of these methods in a robust three-step model identification procedure, which has been used for necessary extraction of pHEMT model parameters.…”

Section: Introductionmentioning

confidence: 99%

Precise Characterization and Multiobjective Optimization of Low Noise Amplifiers

Dobeš¹,

Michal²,

Popp³

et al. 2015

RADIOENGINEERING

View full text Add to dashboard Cite

Although practically all function blocks of the satellite navigation receivers are realized using the CMOS digital integrated circuits, it is appropriate to create a separate low noise antenna preamplifier based on a low noise pHEMT. Such an RF front end can be strongly optimized to attain a suitable tradeoff between the noise figure and transducer power gain. Further, as all the four principal navigation systems (GPS, GLONASS, Galileo, and COMPASS) work in similar frequency bands (roughly from 1.1 to 1.7 GHz), it is reasonable to create the low noise preamplifier for all of them. In the paper, a sophisticated method of the amplifier design is suggested based on multiobjective optimization. A substantial improvement of a standard optimization method is also outlined to satisfy a uniform coverage of Pareto front. Moreover, for enhancing efficiency of many times repeated solutions of large linear systems during the optimization, a new modification of the Markowitz criterion is suggested compatible with fast modes of the LU factorization. Extraordinary attention was also given to the accuracy of modeling. First, an extraction of pHEMT model parameters was performed including its noise part, and several models were compared. The extraction was carried out by an original identification procedure based on a combination of metaheuristic and direct methods. Second, the equations of the passive elements (including transmission lines and T-splitters) were carefully defined using frequency dispersion of their parameters as Q, ESR, etc. Third, an optimal selection of the operating point and essential passive elements was performed using the improved optimization method. Finally, the s-parameters and noise figure of the amplifier were measured, and stability and third-order intermodulation products were also checked.

show abstract

“…For instance, among all kinds of active devices [1,2,3,4], this work pays attention to unity-gain cells (UGCs), not only because of their usefulness to evolve for the creation of more complex analog circuits [14], but also because they are quite useful in implementing linear [1,2] and nonlinear [16,17,18] circuit applications. Henceforth, this work shows a fuzzy-sets-intersection approach to select the optimum W/L sizes of three voltage followers, from an space of feasible solutions which can be computed by metaheuristics [19], swarm [20,21,22] or evolutionary algorithms [23,24,25,26]. To highlight the usefulness of the proposed approach, it is also applied to a bigger active device known as current-feedback operational amplifier (CFOA) [14,15].…”

Section: Introductionmentioning

confidence: 99%

Selection of MOSFET Sizes by Fuzzy Sets Intersection in the Feasible Solutions Space

Polanco-Martagón

Reyes-Salgado

Flores-Becerra

et al. 2012

JART

View full text Add to dashboard Cite

A fuzzy sets intersection procedure to select the optimum sizes of analog circuits composed of metal-oxidesemiconductor field-effect-transistors (MOSFETs), is presented. The cases of study are voltage followers (VFs) and a current-feedback operational amplifier (CFOA), where the width (W) and length (L) of the MOSFETs are selected from the space of feasible solutions computed by swarm or evolutionary algorithms. The evaluation of three objectives, namely: gain, bandwidth and power consumption; is performed using HSPICETM with standard integrated circuit (IC) technology of 0.35μm for the VFs and 180nm for the CFOA. Therefore, the intersection procedure among three fuzzy sets representing “gain close to unity”, ”high bandwidth” and “minimum power consumption”, is presented. The main advantage relies on its usefulness to select feasible W/L sizes automatically but by considering deviation percentages from the desired target specifications. Basically, assigning a threshold to each fuzzy set does it. As a result, the proposed approach selects the best feasible sizes solutions to guarantee and to enhance the performances of the ICs in analog signal processing applications.

show abstract

Evolutionary Algorithms in the Optimal Sizing of Analog Circuits

Cited by 11 publications

References 39 publications

Sizing Analog Integrated Circuits by Current-Branches-Bias Assignments with Heuristics

Sizing Analog Integrated Circuits by Current-Branches-Bias Assignments with Heuristics

Precise Characterization and Multiobjective Optimization of Low Noise Amplifiers

Selection of MOSFET Sizes by Fuzzy Sets Intersection in the Feasible Solutions Space

Contact Info

Product

Resources

About