We report a new InP/GaAsSb double heterojunction bipolar transistor (DHBT) emitter fin architecture with a record f MAX = 1.2 THz, a simultaneous f T = 475 GHz, and BV CEO = 5.4 V. The resulting BV CEO × f MAX = 6.48 THz-V is unparalleled in semiconductor technology. Devices were realized with a 20-nm-thick compositionally and impurity graded GaAsSb-base and a 125-nm InP collector. The performance arises because the process allows: 1) a tunable base-emitter access distance down to 10 nm; 2) the use of thicker base contact metals; and 3) the minimization of parasitic capacitances and resistances via precise lateral wet etching of the base-collector (B/C) mesa. Perhaps more significantly, InP/GaAsSb DHBTs with f MAX ≥ 1 THz are demonstrated with emitter lengths as long as 9.4 μm and areas as high as 1.645 μm 2 . Such an area is >6× larger than previously reported terahertz (THz) DHBTs, representing a breakthrough in THz transistor scalability. This attractive performance level is achieved with a very low dissipated power density which makes InP/GaAsSb DHBTs well-suited for high-efficiency millimeter-and submillimeter-wave applications. Furthermore, we provide the first large-signal characterization of a THz transistor with 94 GHz load-pull measurements showing a peak power-added-efficiency (PAE) of 32.5% (40% collector efficiency) and a maximum saturated power of 6.67 mW/μm 2 or 1.17 mW/μm of emitter length in a common-emitter configuration. Devices operate stably under large-signal conditions, with voltages nearly twice higher than those for peak small-signal performance.

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Part I of this work described narrow bandgap GaInAs-based I-MOS devices with a minimum steep slope SS min = 1.25 mV/dec maintained over 4 orders of magnitude in drain current, I ON /I OFF ratios >10 6 at 300 K (>10 9 at 15 K), and low operating voltages for a gate length of L G = 100 nm. Part II focuses on the device time-domain switching capabilities and RF performance. Digital switching tests using a hybrid connected inverter reveal excellent capabilities for high clock rate operation. Simple circuit estimates indicate that the present 100 nm GaInAs I-MOS can operate with clock frequencies >10 GHz. The impact-ionization-induced hysteresis in the I D -V GS I-MOS characteristics does not play any role in dynamic switching of a digital inverter: the n-channel pull-down transistor turns on with a steep slope, but turns off classically with a higher threshold voltage which reduces the dynamic power dissipation per switching cycle. Factors impacting GaInAs I-MOS reliability are considered, and a physically motivated approach to enhance the reliability of III-V MOSFETs is proposed. We show that GaInAs-based I-MOS devices offer high analog cutoff frequencies and low-noise characteristics, suggesting applicability for digital and RF applications on a single technological platform. When benchmarked against other steep-slope technologies, GaInAs I-MOS shows the strongest steep slope, competitive I ON /I OFF ratios, and lowest operating voltage of any I-MOS transistor to date, without any back-gate/substrate bias.

Indium phosphide (InP)‐based high electron mobility transistors (HEMTs) with an offset gate enable higher maximum oscillation frequency (fMAX) values because of the resulting reduction in gate‐to‐source resistance. Following this approach, improved direct current (DC) characteristics and cutoff frequencies (fT/fMAX > 410/710 GHz with LG = 50 nm) are shown with respect to centered gate devices. However, HEMTs with an offset gate show degraded noise performances compared with centered gate devices because of a higher gate leakage current. The results show that offsetting the gate closer to the source is not desirable for ultra‐low‐noise performance.

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