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In this paper, we describe the development of device models and tools for the design of new transistors such as the carbon nanotube transistor. An HSPICE model for enhancement mode nanotube transistor has been developed. It can be used for design of nanotube transistor circuits as well as to study performance benefits of the new transistor. A model of the carbon nanotube transistor with Schottky barrier is presented. The model enables device design and performance optimization.

The scaling of the MOSFET threshold voltage is limited by the fundamental minimum value of the subthreshold swing, 60 mV/dec at room temperature. This limits the on current as the supply voltage is reduced. Suspended-gate FET (SGFET) [1] features an extremely sharp subthreshold slope and can be used to circumvent this limitation. We present a new, analytical model for the SGFET that is suitable for hand calculations and time-efficient circuit simulations. Our model expresses the pull-in, pull-out voltages and the stable travel range in terms of the structural parameters and the moving gate position as a function of the gate voltage. Starting from our model, we discuss the influence of the structural parameters on the transistor characteristics and the potential of the SGFET for logic circuits. We also introduce the SGFET SRAM cell to demonstrate the use of our model and to illustrate the interest of the SGFET for ultra-low power applications.SGFET combines an electrostatically-actuated NEMS switch with clamped-clamped beam and an inversion-mode MOSFET (Fig. 1). When a gate voltage is applied, the air gap between the gate electrode and the gate oxide is reduced due to the charge-induced electrostatic attraction. The electrostatic force is equilibrated by the elastic force (that can be modeled by a linear spring constant, k [1]) as long as V G is lower than the pullin voltage V pi , leading to a critical gap thickness, x lim . For V G > V pi , the electrostatic component dominates the elastic component and the gate snaps down the gate oxide. When the SGFET is designed such that the mechanical pull-in occurs before the apparition of the inversion channel, extremely sharp on-off transitions become possible. Our SGFET model is therefore focused on this particular operation where the pull-in occurs in weak inversion. This implies Ψ slim < 2Φ F , where Ψ slim is the 'limit surface potential' at pull-in and Φ F is the substrate Fermi potential.Relationships for Ψ slim , x lim ,V pi and x(V G ) are derived by using the force balance equations, depletion approximation and the equation for the limit gap height given in [2] ( Table 1). The variation of the gate position as a function of the gate voltage is shown in Fig. 2, where our analytical model based on the depletion approximation is compared to the iterative solution of the force-balance equation featuring the exact charge equation. It is noticed that our analytical model is in satisfactory agreement with the numerical solution and the difference between the analytically and numerically calculated V pi is about kT/q. In Fig. 2, it can also be remarked that the SGFET exhibits hysteresis, i.e., the gate is pulled-up at a voltage V po < V pi . V po is expressed by using the force equations while the gate is in down-state and neglecting the surface adhesion forces.SGFET analytical model can be used to provide simple design guidelines. For instance a low-voltage operation requires a relatively long beam (Fig. 3a) and/or a reduced gap (Fig. 3b). On the other hand, the substr...